I'm looking for more information on trace length matching for the EPI bus other than what I found on spma056, pg43 which states;
4.11.3 Routing Considerations
In EPI mode, the TM4C129x device pins are characterized with a 35pF output capacitance. To maintain
timing margins over the full operating speed of the EPI module, EPI signal capacitance, including boh load
and trace capacitance, must be 35pF or less, and the GPIO drive strength must be configured for 8mA.
Additionally when EPI0S31 is used as a high speed clock pin, it must be configured to 12mA in order to
maintain timing margins. It is not necessary to include the TM4C129x device pin and pad characteristics
when evaluating total capacitance. Total trace length should be limited to 6 in (15.24 cm) for full operating
speed. Make an effort to keep trace lengths for clock and data similar lengths and give the clock signal 2X
width spacing from other signals to avoid crosstalk.
There is no hard number; any ideas on what has worked in the past maybe?
