SPI for TM4C129ENCPDT

Hello Frank

Please go through the following TI Design Guide for Serial Flash. It uses the connected launchpad EK-TM4C1294XL featuring the TM4C1294NCPDT (which can be swapped by the crypto connected launchpad EK-TM4C129EXL featuring the TM4C129ENCPDT). Also we preferred to use the Macronix Serial Flash for this design. The bare metal serial flash example should be useful for your evaluation.

The code example is in CCS but can be changed for IAR use.

www.ti.com/.../tidu893.pdf

Regards
Amit

Amit

"The bare metal serial flash example should be useful for your evaluation."

"The microSD card uses the Legacy SPI mode of the QSSI module"

There are 6 projects, which one uses the Legacy SPI Mode as referenced in the guide?

Thanks,

Frank

Hello Frank,

The uSD card examples use the legacy SPI Mode (ektm4c129_sdcard_boot_demo1, ektm4c129_sdcard_boot_demo2, ektm4c129_sdcard_bootloader)

The bare metal example for Serial Flash is ektm4c129_qssi_example

Regards
Amit

Amit,

I successfully migrated the "...qssi_example" from CCS to IAR error free. I'm using SSI3 instead of SSI1 and I'm  using the legacy SPI mode with 4 wires so I made the following changes. Is there anything else I should look out for?

Thanks,

Frank

Hello Frank,

Sorry, but I do not see the changes in the post!!!

Regards
Amit

I don't know what happened, I'm using SSI3 instead of SSI1 and I'm using the legacy SPI mode with 4 wires so I made the following changes. Is there anything else I should look out for? Don't I have to indicate legacy mode?

-SSI1 to SSI3
-4 wire to 2 wire SPI

// GPIOPinConfigure(GPIO_PB5_SSI1CLK);
// GPIOPinConfigure(GPIO_PB4_SSI1FSS);
// GPIOPinConfigure(GPIO_PE4_SSI1XDAT0);
// GPIOPinConfigure(GPIO_PE5_SSI1XDAT1);
// GPIOPinConfigure(GPIO_PD4_SSI1XDAT2);
// GPIOPinConfigure(GPIO_PD5_SSI1XDAT3);

//fi remapped
GPIOPinConfigure(GPIO_PQ0_SSI3CLK);
GPIOPinConfigure(GPIO_PQ1_SSI3FSS);
GPIOPinConfigure(GPIO_PQ2_SSI3XDAT0);
GPIOPinConfigure(GPIO_PQ3_SSI3XDAT1);


//
// Configure the GPIO settings for the SSI pins. This function also gives
// control of these pins to the SSI hardware. Consult the data sheet to
// see which functions are allocated per pin.
//

// GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_5 | GPIO_PIN_4);
// GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_5 | GPIO_PIN_4);
// GPIOPinTypeSSI(GPIO_PORTE_BASE, GPIO_PIN_5 | GPIO_PIN_4);

// HWREG(GPIO_PORTB_BASE+GPIO_O_DR8R) |= (GPIO_PIN_5 | GPIO_PIN_4);
// HWREG(GPIO_PORTD_BASE+GPIO_O_DR8R) |= (GPIO_PIN_5 | GPIO_PIN_4);
// HWREG(GPIO_PORTE_BASE+GPIO_O_DR8R) |= (GPIO_PIN_5 | GPIO_PIN_4);


//fi remapped
GPIOPinTypeSSI(GPIO_PORTQ_BASE, GPIO_PIN_1 | GPIO_PIN_0);
GPIOPinTypeSSI(GPIO_PORTQ_BASE, GPIO_PIN_3 | GPIO_PIN_2);
HWREG(GPIO_PORTQ_BASE+GPIO_O_DR8R) |= (GPIO_PIN_1 | GPIO_PIN_0);
HWREG(GPIO_PORTQ_BASE+GPIO_O_DR8R) |= (GPIO_PIN_3 | GPIO_PIN_2);

Hello Frank

The IO Mapping looks correct. Make sure that you have enabled the clock to GPIO Port Q. If you halt the debugger what does the Source window show the CPU is executing.

Note that when using Serial Flash it is important to use the advanced mode and not the legacy mode.

Regards
Amit

Amit,

I'm not sure I know what you mean.........

"Make sure that you have enabled the clock to GPIO Port Q."
?? Is this what you mean

"GPIOPinConfigure(GPIO_PQ0_SSI3CLK);"

or

" SSIConfigSetExpClk(SSI3_BASE, ui32SysClockFreq, SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, (ui32SysClockFreq/2), 8);"

If you halt the debugger what does the Source window show the CPU is executing.
I'll look at that.

Note that when using Serial Flash it is important to use the advanced mode and not the legacy mode.
Is the advance mode compatible w/ Microchip SST26FV032B ?

Since I'm using a 4 wire interface, I should be concentrating on Bi, and not Quad....correct?

Thanks.

Hello Frank

I meant SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ)

If you are using 4 wire interface Advanced and Bi are both possible. Of course Quad is not as it would required SSI3XDAT2 and SSI3XDAT3 pins as well.

Regards
Amit

Amit,

I did include that line. Below is my program...it set's up SSI3 in "Setup_IO()" and attempts to do a simple write of a string (from the Peripheral Driver document).

What I am noticing on my logic analyzer is that the signals MOSI, Enable, & SCLK are clocking but are all the same! MISO is always a logic high, it appears that the setup of my IO is not correct. BTW Freescale (SPI) mode, I believe is important for the SST26VF032B.

Thanks in advance.

void Setup_IO(void)
{

uint32_t ui32SysClockFreq;
ui32SysClockFreq = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
SYSCTL_OSC_MAIN |
SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_480), 120000000);

//
// The SSI1 peripheral must be disabled, reset and re enabled for use.
// Wait till the Peripheral ready is not asserted
//
SysCtlPeripheralDisable(SYSCTL_PERIPH_SSI3);
SysCtlPeripheralReset(SYSCTL_PERIPH_SSI3);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
while(!(SysCtlPeripheralReady(SYSCTL_PERIPH_SSI3)));

//
// For this example SSI3 is used with the following GPIO Pin Mapping
// SSI1CLK : PQ0
// SSI1FSS : PQ1
// SSI1XDAT0 : PQ2
// SSI1XDAT1 : PQ3
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);

//
// Configure the pin muxing for SSI3 functions on port Q[3:0]
//
GPIOPinConfigure(GPIO_PQ0_SSI3CLK);
GPIOPinConfigure(GPIO_PQ1_SSI3FSS);
GPIOPinConfigure(GPIO_PQ2_SSI3XDAT0);
GPIOPinConfigure(GPIO_PQ3_SSI3XDAT1);


//
// Configure the GPIO settings for the SSI pins. This function also gives
// control of these pins to the SSI hardware. Consult the data sheet to
// see which functions are allocated per pin.
//
GPIOPinTypeSSI(GPIO_PORTQ_BASE, GPIO_PIN_1 | GPIO_PIN_0);
GPIOPinTypeSSI(GPIO_PORTQ_BASE, GPIO_PIN_3 | GPIO_PIN_2);
HWREG(GPIO_PORTQ_BASE+GPIO_O_DR8R) |= (GPIO_PIN_1 | GPIO_PIN_0);
HWREG(GPIO_PORTQ_BASE+GPIO_O_DR8R) |= (GPIO_PIN_3 | GPIO_PIN_2);

//
// Configure and enable the SSI port for SPI master mode. Use SSI3,
// system clock supply, idle clock level low and active low clock in
// freescale SPI mode, master mode, 60MHz SSI frequency, and 8-bit data.
// For SPI mode, you can set the polarity of the SSI clock when the SSI
// unit is idle. You can also configure what clock edge you want to
// capture data on. Please reference the datasheet for more information on
// the different SPI modes.
//

//fi remapped to SSI3
SSIConfigSetExpClk(SSI3_BASE, ui32SysClockFreq, SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, (ui32SysClockFreq/2), 8);

//
// Enable the SSI3 module.
//

//fi remapped to SSI3
SSIAdvModeSet(SSI3_BASE,SSI_ADV_MODE_READ_WRITE);
SSIAdvFrameHoldEnable(SSI3_BASE);
HWREG(SSI3_BASE+SSI_O_CR1) |= SSI_CR1_HSCLKEN;
SSIEnable(SSI3_BASE);

}

//*****************************************************************************
//
// Configure SSI3 in master Freescale (SPI) mode. This example will send out
// 256 bytes in Advanced, Bi and Quad Mode and then read the data in Advanced,
// Bi and Quad Mode. Once the data check is completed it shall Erase the Serial
// Flash to return the device to it's original state.
//
//*****************************************************************************
int
main(void)
{

char *pcChars = "SSI Master send data.";
int32_t i32Idx;

Setup_IO();

//
// Send some data.
//
i32Idx = 0;
while(pcChars[i32Idx])
{
SSIDataPut(SSI3_BASE, pcChars[i32Idx]);
i32Idx++;
}

while(1)
;

}

Hello Frank,

The MOSI, SCLK and FSS "would not be the same", unless they have been shorted together and LA misconfigured. Please post a LA scope plot as well.

As for the issue of nothing happening, please read the Serial Flash Data sheet. All data transfers are preceded by commands that must be issued by writing it through the controller.That is what the SSI Bare Metal example does and that is what is missing in your application. A simple SSIDataPut is not sufficient for any serial flash.

Regards
Amit