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Splint half width timers will not configure separately as A - PWM out / B - capture edge count in.

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Other Parts Discussed in Thread: EK-TM4C1294XL

Tivaware text suggest 2 half width timers should be configured separately. When configured timer A/B separately the PWM on timer A stops. PWM regulates fan speed well at this point. The fans tachometer signal need to have edges counted by a timer interrupt that will not interrupt on match count up.

BTW: Seems a Typo in section 13.3.3.3 page 963. That make works well for down-count.

In up-count mode,
the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers. Note
that when executing an up-count, that the value of GPTMTnPR and GPTMTnILR must be greater
than the value of GPTMTnPMR and GPTMTnMATCHR. Table 13-7 on page 963 shows the values
that are loaded into the timer registers when the timer is enabled.

 

The configuration both ways.

 ROM_TimerConfigure(TIMER5_BASE, TIMER_CFG_SPLIT_PAIR |
    		            TIMER_CFG_A_PWM | TIMER_CFG_B_CAP_COUNT_UP);


Seperate TimerConfigs kills PWM and still get no interrupt on B capture edge match count up.

 ROM_TimerConfigure(TIMER5_BASE, TIMER_CFG_SPLIT_PAIR |
    		            TIMER_CFG_A_PWM);


 ROM_TimerConfigure(TIMER5_BASE, TIMER_CFG_SPLIT_PAIR |
                          TIMER_CFG_B_CAP_COUNT_UP);



//! Configures the timer(s).
//!
//! \param ui32Base is the base address of the timer module.
//! \param ui32Config is the configuration for the timer.
//!
//! This function configures the operating mode of the timer(s).  The timer
//! module is disabled before being configured and is left in the disabled
//! state.  The timer can be configured to be a single full-width timer
//! by using the \b TIMER_CFG_* values or a pair of half-width timers using the
//! \b TIMER_CFG_A_* and \b TIMER_CFG_B_* values passed in the \e ui32Config
//! parameter.
//!
//! The configuration is specified in \e ui32Config as one of the following
//! values:
//!
//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer
//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up
//!   instead of down (not available on all parts)
//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer
//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up
//!   instead of down (not available on all parts)
//! - \b TIMER_CFG_RTC - Full-width real time clock timer
//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers
//!
//! When configured for a pair of half-width timers, each timer is separately
//! configured.  The first timer is configured by setting \e ui32Config to
//! the result of a logical OR operation between one of the following values
//! and \e ui32Config:

 

  • Hello BP101,

    Yes, that is correct. The two sub timers need to be configured together for the configuration to be applicable for both sub timers. They cannot be done separately.

    Regards
    Amit
  • Hi Amit,

    So the each part of the same timer can be for a different function without issue?

    The match count interrupt 82 from GPIO pin 71 edge event is not vectoring into the handler after 60 edges counted.

    Edge count timer can be configured for down count but Tivaware only has _count_up or _count --- is the latter down count?

    My configuration - see any errors?

        // PWM-0 duty cycle mode:
        // Enable pin PM6 (MPU-72) for TIMER5A T5CCP0 PWM-0
        ROM_GPIOPinConfigure(GPIO_PM6_T5CCP0);
        ROM_GPIOPinTypeTimer(GPIO_PORTM_AHB_BASE, GPIO_PIN_6);
        // Taco edge count mode:
        // Enable pin PM7 (MPU-71) for TIMER5B T5CCP1 PWM
        ROM_GPIOPinConfigure(GPIO_PM7_T5CCP1);
        ROM_GPIOPinTypeTimer(GPIO_PORTM_AHB_BASE, GPIO_PIN_7);
    
    
        /**********************************************************
         * Timer-5B Fan Tacho CCP1 24 bit up counter PM7-Pin71
         **********************************************************/
    
        /* Set the load timer GPTMTbILR value to count 0x00 up to
         * 60 edges set in GPTMTbMATCHR */
        ROM_TimerLoadSet(TIMER5_BASE, TIMER_B, 0x00);
    
        /* Set the value for the PWM modulator reload interrupt */
        ROM_TimerIntEnable(TIMER5_BASE, TIMER_TIMB_MATCH);
        ROM_TimerEnable(TIMER5_BASE, TIMER_B);
        ROM_IntEnable(INT_TIMER5B);
    
        /* Set Timer-5B match character value GPTMTbMATCHR
         * count-up to 60 edges CCP1 Pin 71 taco interrupt. */
        ROM_TimerMatchSet(TIMER5_BASE, TIMER_B,  0x003C);
    
        /* Configure signal edge(s) that triggers events for CCP1 capture mode. */
        ROM_TimerControlEvent(TIMER5_BASE, TIMER_B, TIMER_EVENT_BOTH_EDGES);
    
        /* Preform an GPTMTAMR Reg0x4 timer5 update on
         * match character and GPTMTbPR load regisers */
        TimerUpdateMode(TIMER5_BASE, TIMER_B, TIMER_UP_MATCH_IMMEDIATE); //TIMER_UP_LOAD_IMMEDIATE
    
        /* Synchronizes the counters in a specified set of timers.
         * Running in half-width mode, each half can be included or
         * excluded in the synchronization event. */
        TimerSynchronize(TIMER5_BASE, TIMER_5A_SYNC | TIMER_5B_SYNC);
    

  • Hello BP101,

    Yes that is correct. However I am not sure why Synchronize is being done. The Synchronize function is for multiple timers in the same mode (AFAIK).

    Regards
    Amit
  • Hi Amit,
    It seems the GPIO pin PM7 is for some reason shorting out the taco signal when it is connected.

    Ok - AFAIK so like both timers would be in PWM mode. Was thinking that it syncs each 1/2 time base as to have PWM T5TCCP0 output occur near in sync with edge capture count event on T5TCCP1.

    Wonder why T5CCP1 thinks its an output or possibly not configured versus timer5B input edge mode?
  • Hello BP101

    Check if the traces are not getting coupled.

    Regards
    Amit
  • Hi Amit,

    Opps now see a pin error. Recently moved the single pin X11-80 PP5 to X11-pin71 thinking was MCU pin 71 or PM7 but is PP0. Seems PM7 would be X11-86. Thanks that's a good find.

    Possible a good thing was not using a level shifter and taco circuit has a voltage divider 6.8k series resistor 22k to ground being taco is open collector needs a 10k pull up.

    Oddly with a +3v3 powering 10k pull up we get 1.9v logic high into GPIO pin, will trigger an interrupt. Same circuit +5v0 10k pull up the high logic level shifts to 2.8v. That 1.9v is well below the GPIO input threshold listed at 0.68v*VDD=2.244v minimum. Seems 0.68v is a tad high for the minimum when VDD=3v3. Wonder what or if the TM4C projected 10 year GPIO threshold has made that 0.68v a higher factor?

  • Hello BP101

    Do look for overshoots on the GPIO pin.

    Regards
    Amit
  • Hi Amit,

    Verify 1.9v taco worked on PP5 triggered discrete interrupt. 1.9v high level but 24v fan with an open collector output, well LVT could provide some protection in that case it ever went into burn out mode.

    Sadly report both timer interrupts 5A/B are not vectoring and match count PWM value set occurs only during timer initialization.
    Changed 5B interrupt to ROM_TimerIntEnable(TIMER5_BASE, TIMER_CAPB_MATCH) still will not vector into handler.
    Both interrupt handlers have exports in startup_ccs.c , lost as to why both timer 5A/B will not set the NVIC interrupt on match count.
  • Hello BP101,

    Can we check if the Interrupt bits do get set if say 60 toggles are generated? That will tell us if the timer is generating the interrupt request to the CPU's NVIC.

    Regards
    Amit
  • Hi Amit,

    Don't think either TM5A/B is interrupting,  have planted UARTprintf messages in each handler  for a match count verify. PWM counts down to GPTMTaMATCHR , that is fan blows 6300 RPM on POR then slows 600 RPM after a continuous PWM signal. Timer5 is also set ALTCLK POIS 16mHz 62.5us Tc.  Calculation suggest 4kHz max edge times and fan taco ranges from 205Hz 6300 RPM to 96Hz or less at very low speed.

    Something maybe in both GPIO pin configurations as PP5 discrete pin taco interrupt was vectoring prior to setting up an edge counter timer.

     PP5 Config:

    // Enable pin PP5 (MCU-106) Fan tachometer discrete INT pin.
     ROM_GPIOPinConfigure(GPIO_PIN_5);
     ROM_GPIOPinTypeGPIOInput(GPIO_PORTP0_AHB_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD_WPU);
     MAP_GPIODirModeSet(GPIO_PORTP0_AHB_BASE, GPIO_PIN_5, GPIO_DIR_MODE_IN);

  • Hello BP101

    What is the PP5 pin configuration for? If it is for GPIO mode then it must be as follows

    ROM_GPIOPinTypeGPIOInput(GPIO_PORTP0_AHB_BASE, GPIO_PIN_5);
    HWREG(GPIO_PORTP0_AHB_BASE+GPIO_O_PUR) |= GPIO_PIN_5;

    Regards
    Amit
  • Hi Amit,

    That is an interesting way to configure discrete per pin interrupt. Didn't want to disable all the other unused port P interrupts. Perhaps that again was not made very clear. Seems the warning was if a discrete pin interrupt is configured and asserted on a single pin then port wide interrupt is no loner possible. And when port wide is selected on GPIO PP0/PQ0 pins we then must disable all single pin interrupts. So the HWREG |= gets around that port wide issue,

    PP5 was being used to assert the same interrupt handler as timer B is not doing but PP5 has since been removed. It seems A is getting RIS interrupt captured mode event and both timers are set PWM mode.

    Debug on timers:

  • Hello BP101

    I am really losing track here on this post.

    1. What is the function of PP5 in this code?
    2. How have the Timer5B Pin configured
    3. Which TM4C device is it.
    4. Did you try stand alone first for timer in capture mode?

    I think a logical path to the final code shall be more useful.

    Regards
    Amit
  • Hi Amit,

    1. Not using PP5 any longer so forget about that. PP5 did prove the taco signal from the fan can cause an interrupt vector into the same handler that timer 5B will not. The NVIC is masked with  INT81/TM5A and INT82/TM5B ready to trigger but that never happens for either timer half.

    2. Timers 5A/5B SW reposted below but the match count interrupt is failing on timer 5A/B.

    3. TM4C1294NCPDTI3 on a EK-TM4C1294XL.

    4. Debug shows both timers are configured for PWM interrupt. Does that seem proper when set interrupt A match count and B interrupt capture mode?

  • Hello BP101,

    I would not be concerned with the PWM Interrupt Enable being set for the 2 timers.

    I also see that the Capture mode is count up (0 to 60) with match being set at 0 and interrupt type as match interrupt. Did you change the Match Count to be something other than 0?

    Regards
    Amit
  • Hi Amit,
    > Did you change the Match Count to be something other than 0?

    Yes tried reversing the load and match count values and making them both the same 0x3C. Nothing will trip the interrupt. Text states the up count automatically resets to 0x00 when matched count 0x3C is reached. Therefore it seemed plausible to match set 0x00 so the interrupt should occur on the next Tc when the timer resets to 0x00.

    Yet that still doesn't explain why both timer interrupts 81 and 82 are not triggering.