Other Parts Discussed in Thread: TM4C1294NCPDT
I'm trying to implement an SPI reader on a TM4C1294XL Launchpad. To do this I opted to plug into SSI3 as the pins are nicely exposed on booster pack 2. My SPI master sends 10 to 122 bytes every 16.66 ms with SCLK driven at 32 MHz.
My original thought is that by setting up the DMA receive properly, I would get an interrupt whenever CS would go back to high with all of the data from that transfer written in memory. At that point I should have about 16.66 ms before the next interrupt goes through. The longest transfer should take a total of 122 * 8 * 0.00003125 = 0.0305 ms. Anyway, I'm going to show my code and wiring later but I'm not getting the behavior I expect, here are the problems I'm having:
- The program is constantly servicing ISRs. The main code never seems to run. In the terms of the code, the receive count is constantly increasing but the read count never goes higher than zero. I'm not sure why this is the case because as mentioned above, there should be ~16 ms of time with no interrupt.
- I don't appear to be getting an interrupt until the 1024 byte buffer is completely full. Does DMA trigger an interrupt when CS goes back to high or not? Should I be using a different interrupt?
- The buffer seems to be filling up with values of 0xFF. I know for a fact that other values are being sent.
Here is the wiring:
Green: CS
Purple: MOSI
Blue: MISO
Yellow: SCLK
White: GND
Orange: 5v
And the code is as follows:
//*****************************************************************************
//
// udma_demo.c - uDMA example.
//
// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2.1.0.12573 of the EK-TM4C1294XL Firmware Package.
//
//*****************************************************************************
#include <stdint.h>
#include <stdbool.h>
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_uart.h"
#include "inc/hw_ssi.h"
#include "driverlib/fpu.h"
#include "driverlib/gpio.h"
#include "driverlib/interrupt.h"
#include "driverlib/pin_map.h"
#include "driverlib/rom.h"
#include "driverlib/rom_map.h"
#include "driverlib/sysctl.h"
#include "driverlib/systick.h"
#include "driverlib/uart.h"
#include "driverlib/udma.h"
#include "driverlib/ssi.h"
#include "utils/uartstdio.h"
#include "utils/ustdlib.h"
//*****************************************************************************
//
//! \addtogroup example_list
//! <h1>uDMA (udma_demo)</h1>
//!
//! This example application demonstrates the use of the uDMA controller to
//! transfer data between memory buffers, and to transfer data to and from a
//! UART. The test runs for 10 seconds before exiting.
//!
//! UART0, connected to the ICDI virtual COM port and running at 115,200,
//! 8-N-1, is used to display messages from this application.
//
//*****************************************************************************
//****************************************************************************
//
// System clock rate in Hz.
//
//****************************************************************************
uint32_t g_ui32SysClock;
#define UDMA_CHANNEL_SSI3RX 14
#define UDMA_CHANNEL_SSI3TX 15
//*****************************************************************************
//
// The size of the memory transfer source and destination buffers (in words).
//
//*****************************************************************************
#define SSI_BUFFER_SIZE 1024
#define SSI_RX_BUFFER_COUNT 5
//*****************************************************************************
//
// The SSI3 Buffers
//
//*****************************************************************************
static uint8_t g_ui8SSITxBuf[SSI_BUFFER_SIZE];
static uint8_t g_ui8SSIRxBuf[SSI_RX_BUFFER_COUNT][SSI_BUFFER_SIZE];
//*****************************************************************************
//
// The Memory Control Variables
//
//*****************************************************************************
static uint32_t g_ui32MessageSizes[SSI_RX_BUFFER_COUNT];
static uint8_t g_ui8RxWriteIndex = 0;
static uint8_t g_ui8RxReadIndex = 0;
//*****************************************************************************
//
// The count of uDMA errors. This value is incremented by the uDMA error
// handler.
//
//*****************************************************************************
static uint32_t g_ui32uDMAErrCount = 0;
//*****************************************************************************
//
// The count of SSI3 buffers filled/read
//
//*****************************************************************************
static uint32_t g_ui32SSIRxWriteCount = 0;
static uint32_t g_ui32SSIRxReadCount = 0;
static uint32_t g_ui32SSITxCount = 0;
//*****************************************************************************
//
// The control table used by the uDMA controller. This table must be aligned
// to a 1024 byte boundary.
//
//*****************************************************************************
#if defined(ewarm)
#pragma data_alignment=1024
uint8_t pui8ControlTable[1024];
#elif defined(ccs)
#pragma DATA_ALIGN(pui8ControlTable, 1024)
uint8_t pui8ControlTable[1024];
#else
uint8_t pui8ControlTable[1024] __attribute__ ((aligned(1024)));
#endif
//*****************************************************************************
//
// The error routine that is called if the driver library encounters an error.
//
//*****************************************************************************
#ifdef DEBUG
void
__error__(char *pcFilename, uint32_t ui32Line)
{
}
#endif
//*****************************************************************************
//
// The interrupt handler for uDMA errors. This interrupt will occur if the
// uDMA encounters a bus error while trying to perform a transfer. This
// handler just increments a counter if an error occurs.
//
//*****************************************************************************
void
uDMAErrorHandler(void)
{
uint32_t ui32Status;
//
// Check for uDMA error bit
//
ui32Status = ROM_uDMAErrorStatusGet();
//
// If there is a uDMA error, then clear the error and increment
// the error counter.
//
if(ui32Status)
{
ROM_uDMAErrorStatusClear();
g_ui32uDMAErrCount++;
}
}
//*****************************************************************************
//
// SSI3 Interrupt Handler
//
//*****************************************************************************
void SSI3IntHandler(void) {
uint32_t ui32Status;
uint32_t ui32Mode;
ui32Status = ROM_SSIIntStatus(SSI3_BASE, 1);
ROM_SSIIntClear(SSI3_BASE, ui32Status);
ui32Mode = ROM_uDMAChannelModeGet(UDMA_CHANNEL_SSI3RX | UDMA_PRI_SELECT);
if(ui32Mode == UDMA_MODE_STOP) {
//Calculate next RxWriteIndex (buffer in which to write the next set of data)
uint8_t nextIndex = g_ui8RxWriteIndex + 1;
if(nextIndex >= SSI_RX_BUFFER_COUNT) nextIndex = 0;
//Write out the size of the completed transfer
uint32_t xferSize = ROM_uDMAChannelSizeGet(UDMA_CHANNEL_SSI3RX | UDMA_PRI_SELECT);
g_ui32MessageSizes[g_ui8RxWriteIndex] = SSI_BUFFER_SIZE - xferSize - 1;
UARTprintf("%d\t%d\t%x\n", g_ui8RxWriteIndex, g_ui32MessageSizes[g_ui8RxWriteIndex], g_ui8SSIRxBuf[g_ui8RxWriteIndex][2]);
//Move current rx write index to the next buffer
g_ui8RxWriteIndex = nextIndex;
//Enable DMA channel to write in the next buffer position
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI3RX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *)(SSI3_BASE + SSI_O_DR),
g_ui8SSIRxBuf[g_ui8RxWriteIndex], sizeof(g_ui8SSIRxBuf[g_ui8RxWriteIndex]));
ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI3RX);
//Increment receive count
g_ui32SSIRxWriteCount++;
}
if(!ROM_uDMAChannelIsEnabled(UDMA_CHANNEL_SSI3TX)) {
g_ui32SSITxCount++;
//Enable DMA channel to write in the next buffer position
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI3TX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, g_ui8SSITxBuf,
(void *)(SSI3_BASE + SSI_O_DR),
sizeof(g_ui8SSITxBuf));
ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI3TX);
}
}
void ConfigureDMA(void) {
//
// Enable the uDMA controller at the system level. Enable it to continue
// to run while the processor is in sleep.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA);
//
// Enable the uDMA controller error interrupt. This interrupt will occur
// if there is a bus error during a transfer.
//
ROM_IntEnable(INT_UDMAERR);
//
// Enable the uDMA controller.
//
ROM_uDMAEnable();
//
// Point at the control table to use for channel control structures.
//
ROM_uDMAControlBaseSet(pui8ControlTable);
//Assign DMA channels to SSI3
ROM_uDMAChannelAssign(UDMA_CH14_SSI3RX);
ROM_uDMAChannelAssign(UDMA_CH15_SSI3TX);
//
// Put the attributes in a known state for the uDMA SSI0RX channel. These
// should already be disabled by default.
//
//TODO: SHOULD THIS BE ENABLE?
ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI3RX,
UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
(UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK));
//ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_SSI3RX, UDMA_ATTR_USEBURST);
//
// Configure the control parameters for the primary control structure for
// the SSIORX channel.
//
ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI3RX | UDMA_PRI_SELECT,
UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 |
UDMA_ARB_4);
//Enable DMA channel to write in the next buffer position
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI3RX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *)(SSI3_BASE + SSI_O_DR),
g_ui8SSIRxBuf[g_ui8RxWriteIndex], sizeof(g_ui8SSIRxBuf[g_ui8RxWriteIndex]));
// Configure TX
//
// Put the attributes in a known state for the uDMA SSI0TX channel. These
// should already be disabled by default.
//
ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI3TX,
UDMA_ATTR_ALTSELECT |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);
//
// Set the USEBURST attribute for the uDMA SSI0TX channel. This will
// force the controller to always use a burst when transferring data from
// the TX buffer to the SSI0. This is somewhat more effecient bus usage
// than the default which allows single or burst transfers.
//
//ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_SSI3TX, UDMA_ATTR_USEBURST);
//
// Configure the control parameters for the primary control structure for
// the SSIORX channel.
//
ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI3TX | UDMA_PRI_SELECT,
UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE |
UDMA_ARB_4);
//Configure TX to always write 0xFF?
g_ui8SSITxBuf[0] = 0xFF;
//Enable DMA channel to write in the next buffer position
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI3TX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, g_ui8SSITxBuf,
(void *)(SSI3_BASE + SSI_O_DR),
sizeof(g_ui8SSITxBuf));
ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI3RX);
ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI3TX);
//
// Enable the SSI3 DMA TX/RX interrupts.
//
ROM_SSIIntEnable(SSI3_BASE, SSI_DMATX | SSI_DMARX);
//
// Enable the SSI3 peripheral interrupts.
//
ROM_IntEnable(INT_SSI3);
}
void ConfigureSSI3(void) {
//
// Enable the SSI3 Peripheral.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_SSI3);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
// Configure GPIO Pins for SSI3 mode.
//
ROM_GPIOPinConfigure(GPIO_PQ0_SSI3CLK);
ROM_GPIOPinConfigure(GPIO_PQ1_SSI3FSS);
ROM_GPIOPinConfigure(GPIO_PQ2_SSI3XDAT0);
ROM_GPIOPinConfigure(GPIO_PQ3_SSI3XDAT1);
ROM_GPIOPinTypeSSI(GPIO_PORTQ_BASE, GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0);
ROM_SSIConfigSetExpClk(SSI3_BASE, g_ui32SysClock, SSI_FRF_MOTO_MODE_0,
SSI_MODE_SLAVE, 5333333, 8);
ROM_SSIEnable(SSI3_BASE);
ROM_SSIDMAEnable(SSI3_BASE, SSI_DMA_RX | SSI_DMA_TX);
}
//*****************************************************************************
//
// Configure the UART and its pins. This must be called before UARTprintf().
//
//*****************************************************************************
void ConfigureUART(void) {
//
// Enable the GPIO Peripheral used by the UART.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
//
// Enable UART0
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UART0);
//
// Configure GPIO Pins for UART mode.
//
ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
//
// Initialize the UART for console I/O.
//
UARTStdioConfig(0, 115200, g_ui32SysClock);
}
//*****************************************************************************
//
// This example demonstrates how to use the uDMA controller to transfer data
// between memory buffers and to and from a peripheral, in this case a UART.
// The uDMA controller is configured to repeatedly transfer a block of data
// from one memory buffer to another. It is also set up to repeatedly copy a
// block of data from a buffer to the UART output. The UART data is looped
// back so the same data is received, and the uDMA controlled is configured to
// continuously receive the UART data using ping-pong buffers.
//
// The processor is put to sleep when it is not doing anything, and this allows
// collection of CPU usage data to see how much CPU is being used while the
// data transfers are ongoing.
//
//*****************************************************************************
int main(void) {
//
// Set the clocking to run directly from the crystal at 120MHz.
//
g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
SYSCTL_OSC_MAIN |
SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_480), 120000000);
//
// Enable peripherals to operate when CPU is in sleep.
//
ROM_SysCtlPeripheralClockGating(true);
//
// Enable the GPIO port that is used for the on-board LED.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
//
// Enable the GPIO port that is used for the SSI chip select
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
//
// Enable the GPIO pins for the LED (PN0).
//
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_0);
//
// Initialize the UART.
//
ConfigureUART();
UARTprintf("\033[2J\033[H");
UARTprintf("uDMA Example\n");
//
// Initialize SSI3.
//
ConfigureSSI3();
//
// Show the clock frequency on the display.
//
UARTprintf("Tiva C Series @ %u MHz\n\n", g_ui32SysClock / 1000000);
//
// Initialize DMA
//
ConfigureDMA();
//
// Loop forever printing 1 message for every 60
//
int count = 0;
while(1)
{
if(g_ui32SSIRxReadCount < g_ui32SSIRxWriteCount) {
//If this condition is met, a message has been written to a buffer but not yet read
if(count == 0) {
//If this condition is met this is the first message out of a count of 60, print the message
uint32_t messageSize = g_ui32MessageSizes[g_ui8RxReadIndex];
UARTprintf("[%u] ", messageSize);
int i;
for(i = 0; i < messageSize; i++) {
UARTprintf("%x ", g_ui8SSIRxBuf[g_ui8RxReadIndex][i]);
}
UARTprintf("\n");
}
g_ui8RxReadIndex++;
if(g_ui8RxReadIndex >= SSI_RX_BUFFER_COUNT) g_ui8RxReadIndex = 0;
g_ui32SSIRxReadCount++; //Increment read count
count++;
if(count >= 60) count = 0;
}
}
}
//*****************************************************************************
//
// Startup code for use with TI's Code Composer Studio.
//
// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
//*****************************************************************************
#include <stdint.h>
//*****************************************************************************
//
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
void ResetISR(void);
static void NmiSR(void);
static void FaultISR(void);
static void IntDefaultHandler(void);
//*****************************************************************************
//
// External declaration for the reset handler that is to be called when the
// processor is started
//
//*****************************************************************************
extern void _c_int00(void);
//*****************************************************************************
//
// Linker variable that marks the top of the stack.
//
//*****************************************************************************
extern uint32_t __STACK_TOP;
//*****************************************************************************
//
// External declarations for the interrupt handlers used by the application.
//
//*****************************************************************************
extern void uDMAErrorHandler(void);
extern void SSI3IntHandler(void);
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000 or at the start of
// the program if located at a start address other than 0.
//
//*****************************************************************************
#pragma DATA_SECTION(g_pfnVectors, ".intvecs")
void (* const g_pfnVectors[])(void) =
{
(void (*)(void))((uint32_t)&__STACK_TOP),
// The initial stack pointer
ResetISR, // The reset handler
NmiSR, // The NMI handler
FaultISR, // The hard fault handler
IntDefaultHandler, // The MPU fault handler
IntDefaultHandler, // The bus fault handler
IntDefaultHandler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
IntDefaultHandler, // SVCall handler
IntDefaultHandler, // Debug monitor handler
0, // Reserved
IntDefaultHandler, // The PendSV handler
IntDefaultHandler, // The SysTick handler
IntDefaultHandler, // GPIO Port A
IntDefaultHandler, // GPIO Port B
IntDefaultHandler, // GPIO Port C
IntDefaultHandler, // GPIO Port D
IntDefaultHandler, // GPIO Port E
IntDefaultHandler, // UART0 Rx and Tx
IntDefaultHandler, // UART1 Rx and Tx
IntDefaultHandler, // SSI0 Rx and Tx
IntDefaultHandler, // I2C0 Master and Slave
IntDefaultHandler, // PWM Fault
IntDefaultHandler, // PWM Generator 0
IntDefaultHandler, // PWM Generator 1
IntDefaultHandler, // PWM Generator 2
IntDefaultHandler, // Quadrature Encoder 0
IntDefaultHandler, // ADC Sequence 0
IntDefaultHandler, // ADC Sequence 1
IntDefaultHandler, // ADC Sequence 2
IntDefaultHandler, // ADC Sequence 3
IntDefaultHandler, // Watchdog timer
IntDefaultHandler, // Timer 0 subtimer A
IntDefaultHandler, // Timer 0 subtimer B
IntDefaultHandler, // Timer 1 subtimer A
IntDefaultHandler, // Timer 1 subtimer B
IntDefaultHandler, // Timer 2 subtimer A
IntDefaultHandler, // Timer 2 subtimer B
IntDefaultHandler, // Analog Comparator 0
IntDefaultHandler, // Analog Comparator 1
IntDefaultHandler, // Analog Comparator 2
IntDefaultHandler, // System Control (PLL, OSC, BO)
IntDefaultHandler, // FLASH Control
IntDefaultHandler, // GPIO Port F
IntDefaultHandler, // GPIO Port G
IntDefaultHandler, // GPIO Port H
IntDefaultHandler, // UART2 Rx and Tx
IntDefaultHandler, // SSI1 Rx and Tx
IntDefaultHandler, // Timer 3 subtimer A
IntDefaultHandler, // Timer 3 subtimer B
IntDefaultHandler, // I2C1 Master and Slave
IntDefaultHandler, // CAN0
IntDefaultHandler, // CAN1
IntDefaultHandler, // Ethernet
IntDefaultHandler, // Hibernate
IntDefaultHandler, // USB0
IntDefaultHandler, // PWM Generator 3
IntDefaultHandler, // uDMA Software Transfer
uDMAErrorHandler, // uDMA Error
IntDefaultHandler, // ADC1 Sequence 0
IntDefaultHandler, // ADC1 Sequence 1
IntDefaultHandler, // ADC1 Sequence 2
IntDefaultHandler, // ADC1 Sequence 3
IntDefaultHandler, // External Bus Interface 0
IntDefaultHandler, // GPIO Port J
IntDefaultHandler, // GPIO Port K
IntDefaultHandler, // GPIO Port L
IntDefaultHandler, // SSI2 Rx and Tx
SSI3IntHandler, // SSI3 Rx and Tx
IntDefaultHandler, // UART3 Rx and Tx
IntDefaultHandler, // UART4 Rx and Tx
IntDefaultHandler, // UART5 Rx and Tx
IntDefaultHandler, // UART6 Rx and Tx
IntDefaultHandler, // UART7 Rx and Tx
IntDefaultHandler, // I2C2 Master and Slave
IntDefaultHandler, // I2C3 Master and Slave
IntDefaultHandler, // Timer 4 subtimer A
IntDefaultHandler, // Timer 4 subtimer B
IntDefaultHandler, // Timer 5 subtimer A
IntDefaultHandler, // Timer 5 subtimer B
IntDefaultHandler, // FPU
0, // Reserved
0, // Reserved
IntDefaultHandler, // I2C4 Master and Slave
IntDefaultHandler, // I2C5 Master and Slave
IntDefaultHandler, // GPIO Port M
IntDefaultHandler, // GPIO Port N
0, // Reserved
IntDefaultHandler, // Tamper
IntDefaultHandler, // GPIO Port P (Summary or P0)
IntDefaultHandler, // GPIO Port P1
IntDefaultHandler, // GPIO Port P2
IntDefaultHandler, // GPIO Port P3
IntDefaultHandler, // GPIO Port P4
IntDefaultHandler, // GPIO Port P5
IntDefaultHandler, // GPIO Port P6
IntDefaultHandler, // GPIO Port P7
IntDefaultHandler, // GPIO Port Q (Summary or Q0)
IntDefaultHandler, // GPIO Port Q1
IntDefaultHandler, // GPIO Port Q2
IntDefaultHandler, // GPIO Port Q3
IntDefaultHandler, // GPIO Port Q4
IntDefaultHandler, // GPIO Port Q5
IntDefaultHandler, // GPIO Port Q6
IntDefaultHandler, // GPIO Port Q7
IntDefaultHandler, // GPIO Port R
IntDefaultHandler, // GPIO Port S
IntDefaultHandler, // SHA/MD5 0
IntDefaultHandler, // AES 0
IntDefaultHandler, // DES3DES 0
IntDefaultHandler, // LCD Controller 0
IntDefaultHandler, // Timer 6 subtimer A
IntDefaultHandler, // Timer 6 subtimer B
IntDefaultHandler, // Timer 7 subtimer A
IntDefaultHandler, // Timer 7 subtimer B
IntDefaultHandler, // I2C6 Master and Slave
IntDefaultHandler, // I2C7 Master and Slave
IntDefaultHandler, // HIM Scan Matrix Keyboard 0
IntDefaultHandler, // One Wire 0
IntDefaultHandler, // HIM PS/2 0
IntDefaultHandler, // HIM LED Sequencer 0
IntDefaultHandler, // HIM Consumer IR 0
IntDefaultHandler, // I2C8 Master and Slave
IntDefaultHandler, // I2C9 Master and Slave
IntDefaultHandler, // GPIO Port T
IntDefaultHandler, // Fan 1
0, // Reserved
};
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called. Any fancy
// actions (such as making decisions based on the reset cause register, and
// resetting the bits in that register) are left solely in the hands of the
// application.
//
//*****************************************************************************
void
ResetISR(void)
{
//
// Jump to the CCS C initialization routine. This will enable the
// floating-point unit as well, so that does not need to be done here.
//
__asm(" .global _c_int00\n"
" b.w _c_int00");
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a NMI. This
// simply enters an infinite loop, preserving the system state for examination
// by a debugger.
//
//*****************************************************************************
static void
NmiSR(void)
{
//
// Enter an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives a fault
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void
FaultISR(void)
{
//
// Enter an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void
IntDefaultHandler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
