Timers 5A/B split 1/2 width mode - PWM out and Edge capture will not assert either timer interrupt on match count.

Hello BP101,

I can try the code on Monday on my connected LP to see what the issue. Please do share the Pin Configuration as well.

Regards
Amit

Hi Amit,

Thanks that would be helpful to understand where logic is going amuck.

TM5A/B interrupts registered (startup_ccs.c) and was going to try adding TimerIntRegister() even though debug presently show both TM5A/B GPTMIMR registered into global NVIC bits 65,66.

PWM signal is verified on oscilloscope and reloads on match count yet no interrupt. Changes to duty % will change the fan speed but only once during initialization. Edge count in my view would benefit off loading taco signal to HW timer versus only SW with NVIC interrupts 60 times per second. The main reason for attempting to capture the taco edges via HW. Fan speed control is fun to design other sensor constraints around.

Your code:

   ROM_TimerConfigure(TIMER5_BASE, TIMER_CFG_SPLIT_PAIR |  TIMER_CFG_A_PWM | TIMER_CFG_B_CAP_COUNT_UP);

causes one of the split (not splint) timers to count "down" (PWM one) and the other to count up.   Might that confound (surely complicate) any interrupt?

Thru observation - counting up is most always - more problemmatic than counting down.   Switching split timer B to count down eliminates this (potential) issue...

Would not your issue yield to simple, single, split timer, interrupt test/verify?   Prove a single split timer works - only then move to the 2nd - and only then enable - then test/verify both.

KISS has been around longer than you/Amit/moi - given (chance/2) it has terrific record of success...   (Gurus should be able & resourceful experimenters - not endless requesters...And staff asks, "Has he (really) run out of Timers?" - such that you must "overwork" Timer5?)

Hello BP101,

Are you trying to control a 4 wire PC fan?

Regards
Amit

Buoyed by Amit's response - I checked our firm's (5 year past) code which also employed Split Timers.   Found that indeed you're correct that different interrupts may be generated for each of the (same base) split timers.  

Yet - we were conservative - and never caused interrupts across both split timers.   Looking more closely now - I believe this is possible - and as Amit argued earlier - your set-up & config of both split timers rises to, "Likely suspect."

And still we believe that KISS - One Split Timer at a time - is the fastest/safest means to fully resolve...

Hi Amit,

Yes is 4 wire PWM with tachometer.

 Registering the 2 interrupts didn't make any difference on my end. 

I simply put a UARTprintf()  message in each handler to know when the interrupt vector triggers and have a fan connected as well.

The interrupts should be firing since the timers are counting change PWM duty cycle and both are matching CHR on down or up count.

Thanks for timers input CB1 :)

Hi CB1,

Second time try last post bounced by side back mouse button,.

>Switching split timer B to count down eliminates this (potential) issue...

Down count is more complicated, does not auto reset TMxEN on match CHR. Timer up count auto resets TMxEN on match CHR and auto loads the count register xILR with 0x00. May have to split them if Amit also gets the same results. Seems that other configuration is required to make it all well oiled. The PWM part is part done but unless using lookup tables to set fan speed is the goal dynamic throttle is most clunky without interrupts.

Hello BP101,

OK. Thought so as well. Anyways I would have some time to test the code to see if interrupts come out as expected.

Regards
Amit

Hi Amit,

Separated the timers per CB1 suggestion and still the CCP0 pin will not set interrupt on either timer. Perhaps TimerConfigure assert is not allowing the configuration to set UP count on a split pair. The != split pair in lower assert seems to point the upper Assert takes precedence and makes them both interrupt PWM or what ever ends up being the assert.

void
TimerConfigure(uint32_t ui32Base, uint32_t ui32Config)
{
    //
    // Check the arguments.
    //
    ASSERT(_TimerBaseValid(ui32Base));
    ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) ||
           (ui32Config == TIMER_CFG_ONE_SHOT_UP) ||
           (ui32Config == TIMER_CFG_PERIODIC) ||
           (ui32Config == TIMER_CFG_PERIODIC_UP) ||
           (ui32Config == TIMER_CFG_RTC) ||
           ((ui32Config & 0xff000000) == TIMER_CFG_SPLIT_PAIR));
    ASSERT(((ui32Config & 0xff000000) != TIMER_CFG_SPLIT_PAIR) ||
           ((((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
             ((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) ||
             ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
             ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) ||
             ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
             ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
             ((ui32Config & 0x000000ff) == TIMER_CFG_A_PWM)) &&
            (((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) ||
             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) ||
             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) ||
             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) ||
             ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PWM))));

BP101 said:

... still the CCP0 pin will not set interrupt on either timer.

Are you seeking to interrupt (only) via a toggle upon an MCU external pin?  (even if - and especially if - that pin routes to the timer)

That's a different beast - is it not?   In your earlier writings I had the impression you were after, "Timer Generated Interrupts" - not subject to outside inputs visited upon MCU pins.   (even timer-linked MCU pins)    Beware "shape shifting" ... never fun for hapless helpers...

Hi CB1,
The CCP1 pin input TM5B is configured for an edge capture counting event and a triggered internal interrupt on match count that vectors to a handler. The CCP0 timer 5A PWM generator is configured for an internal match count interrupt vector. Even after setting load values for a 25kHz PWM & 50% duty cycle the reload match on down count never triggers that interrupt as it is expected to.

Unlike edge capture down count PWM down count auto resets the TMbEN so it keeps PWMing after initiate. Produces a very nice 25kHz PWM with 50% duty and the fan runs at about 1350 RPM estimate. Changes to the duty cycle are now and remain static on initiate that is why the interrupt is needed for the update processes. I known you know that but put it here for anyone else wondering why PWM interrupt is needed.

Updated PWM values in the code above.

Hello BP101

I took the code and ran it on a EK-TM4C1294XL. Some notes from the code

1. GPIO_PORTM_AHB_BASE is not a valid define in TivaWare 2.1.1.71
2. For the PWM Mode the interrupt is generated on 3 types of events: Rising, Falling or Both Edge and not on a Timeout or Match. Hence Time5A is not branching to the interrupt handler.
3. I looped back PM6 and PM7 and Timer 5B Interrupt Handler did get invoked.

Regards
Amit

Hi Amit,

1. GPIO_PORTM_AHB_BASE  is a personal fix that sets the proper call sign as AHB high speed port M that Tivaware 2.1.71 did not fix. GPIO Port M-Q are not specifically slow speed GPIO according to TM4C1294NCPDT data sheet.

2.  From my take that is more for use in edge capture PWM monitor mode.  For basic PWM mode TAMR bits are already set in periodic timer mode so TAMIE needs to be set, it is not being configured. I have tried to or  TIMER_TAMR_TAPWMIE | TIMER_TAMR_TAMIE but that is not setting the bit in all this wacky shifting business. We have to be able to reload the timer on match up count order to adjust the duty cycle and it takes and interrupt on match or zero to do that effectively. Otherwise we would have to poll the TAV/TBV registers which defeats the purpose to use a timer for PWM. The idea in my opinion is to off load timer match events in HW interrupts so SW time is put to better use at this 25kHz PWM speed especially.

3.  Does PM6 have a PWM signal on it, mine does. Now 25kHz PWM so I learning the hard way how to set the timer PWM frequency. The new PWM timer values are posted above.

Timers configure need review set TAMIE match interrupt for PWM periodic timer mode. Match count in edges capture mode (Not PWM edges capturee mode) should be possible otherwise how do we let the timer know when the desired number of input edges counted matches our set number other than by interrupt source.

    //
    // Set the configuration of the A and B timers and set the TxPWMIE bit.
    // Note that the B timer configuration is ignored by the hardware in 32-bit
    // modes.
    //
    if(NEW_TIMER_CONFIGURATION)
    {
        HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) |
                                          (ui32Config & 0xff) |
                                          TIMER_TAMR_TAPWMIE | TIMER_TAMR_TAMIE);//10.27.15 TIMER_TAMR_TAMIE
        HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) |
                                          ((ui32Config >> 8) & 0xff) |
                                          TIMER_TBMR_TBPWMIE | TIMER_TBMR_TBMIE);//10.27.15 TIMER_TAMR_TAMIE
    }
    else
    {
        HWREG(ui32Base + TIMER_O_TAMR) = ((ui32Config & 0xff) |
                                          TIMER_TAMR_TAPWMIE | TIMER_TAMR_TAMIE);//10.27.15 TIMER_TAMR_TAMIE
        HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config >> 8) & 0xff) |
                                          TIMER_TBMR_TBPWMIE | TIMER_TBMR_TBMIE);//10.27.15 TIMER_TAMR_TAMIE
    }
}

Hi Amit,

Finally got the edge counter working with match count TAMIE,  part of the issue is the timer configuration is kludged. The other is the BmatchChr register is not 0x0000.0000 on POR is 0x0000.FFFF.  So the match load set has to be 0x003C or the match CHR interrupt never vectors the RAW match int.

I broke down the ui32 configuration to analyze why it was not setting TAMIE on either timer A or B. The configuration is now setting TAMIE on both but TMRA is not interrupting on AmatchChr for what ever reason.  Recently remove the timer control event from TMR-A so it might still need that.

Here is the configuration if you wan tot try it out.

/* Set Timer-5 control register for
 * split half wide 16 bit timers */
 HWREG(TIMER5_BASE + TIMER_O_CFG) = 0x4;
/* Set timer 5B mode register for PWM periodic down count mode with a match PWM count interrupt */
 HWREG(TIMER5_BASE + TIMER_O_TAMR) = (TIMER_CFG_A_PWM | TIMER_TAMR_TAMIE);
/* Set timer 5B mode register for edge capture mode with up match edge count reload interrupt */
 HWREG(TIMER5_BASE + TIMER_O_TBMR) = (TIMER_CFG_B_CAP_COUNT_UP | TIMER_TBMR_TBMR_CAP |
                                             TIMER_TBMR_TBCDIR | TIMER_TBMR_TBMIE);

Hello BP101

Do you mean timer configuration as done by TivaWare is "kludged"? If that is the case then how did I get the same configuration to work!!!

As for the PWM mode interrupt since you want the PWM to load at a specific time, i would suggest using the Edge interrupt being generated by the PWM mode and Load on Timeout instead of Immediate load.

Regards,
Amit

Hi Amit,

The same configuration would not set the seemingly necessary TBMIE interrupt bit in the configuration shown in first post. The configuration for the split mode timers mode to preform edge count matched interrupts will not set the TBMIE bit. Debug clearly shows TBMIE was not set on either timer half and only set the PWM interrupts. What ever that PWM interrupt does is a complete mystery just like EMAC0 interrupt 56 comes from where exactly.

Perhaps the each timers PWM interrupt is somehow asserting the RAW match count interrupt? What number is the PWM interrupt in each timer half since the text does not elaborate that point what it does.  What is the PWM interrupt source number or does it assume each timers half interrupt source value?

The timer block figure 13-1 is not showing the interrupts out from each timer half A/B and depicts it as an output from the Configuration/Interrupt block entering each of the timer counters.

Figure 13-1 Seemingly depicts driving interrupts into the timer counters A/B in the direction of the arrow seems to be drawn incorrectly. Each timer counter chain interrupts the configuration Interrupt block not the other way around. No wonder this is taking days to make the edge counter work as its a bit confusing.

>As for the PWM mode interrupt since you want the PWM to load at a specific time. I would suggest using the Edge interrupt being generated by the PWM mode and Load on Timeout instead of Immediate load.

I don't need to count or capture the PWM edge time and the load immediate was a try to get the PWM interrupt to fire. Using load on timeout will not work in this case to force an dynamic and immediate change in duty cycle. Seemingly we have to force the timers updated load value during the match or load count interrupt cycle. Hence TAMIE once again should save the day.   

Hello BP101

The data sheet shows which section of the interrupt registers in timer belong to which half of the timer.

Note that an immediate load may change the behavior of the PWM itself causing a higher frequency with in correct DC. I have seen that in PWM mode w/o using Load on Timeout.

Regards
Amit

Hi Amit,

>The data sheet shows which section of the interrupt registers in timer belong to which half of the timer.

Ok somewhat limited in brief but the dang arrow is on the wrong end of the stick, points into the timer external control and where is the PWM interrupts going - who knows.  All the PWM section states about the interrupt is being RAW. The biggest problem is expecting TMA to act a bit like the PWM peripheral in the counts loading, albeit TMA limited to count down or up mode relative to interrupt TnPWMIE. Yet the TnMIE is part of that timer and should not be discarded in mode TAAMS(1). Seems PWM mode assumes we want to monitor edge events on the CC0/1 pins - who really knows that part is left out. I have been in both modes with TMA an neither mode will assert an NVIC interrupt 81 bit 65.

The timer is capable of generating interrupts based on three types
of events: rising edge, falling edge, or both.
 (events where?) The event is configured by the TnEVENT field of the GPTMCTL register,
and the interrupt is enabled by setting the TnPWMIE bit in the
GPTMTnMR register. When the event occurs, the CnERIS bit is set in the GPTM Raw Interrupt
Status (GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear
(GPTMICR) register

>w/o using Load on Timeout

Like to get TMA interrupt to trigger when the count is matched so it vectors into the handler. The TAMIE interrupt appear to disable when TMA is set alternate mode TAAMS(1) due to the CCP0 output pin PWM. So how can PWM interrupt be used to vector into a handler

Hi Amit,
One other thing - timer A mode register 2 attempts to explain PWM interrupt use, TAPWMIE enables edge capture mode interrupt. We know that typically has nothing to do with timeout or match interrupts. Question is why does TAAMS(1) cut off all the other timer interrupt sources other than PWM edge capture interrupt. If 1/2 the timer can be used to produce PWM in TAAMS(0) and still have output on the CCP0 pin we may have a WA not discussed in the datasheet.

Oddly no typical masked interrupt sources will fire when TAAMS(1) other the PWM capture interrupt. Not even if TACINTD(1) periodic count mode will a count timeout assert a masked interrupt source. I made sure the timer was in one-shot/periodic interrupt mode TACINTD(1). RAW interrupt CAERIS is the only source that asserts in TAAMS(1).
If the load/match values were incorrect there shouldn't be 25Khz PWM on the GPIO pin.

Hello BP101

What is TMA?

Regards
Amit

Hello BP101,

Yes, it is rather very confusing that the interrupt is generated only on edges but not on Timeout or Match. But the way of looking at it is that the user knows that the PWM signal toggles at Match and Timeout. So instead of checking on TO and Match to be used as a change and when output is inverted have the opposite effect, making it Edge sensitive puts out more value.

Regards
Amit

Hi Amit,

>What is TMA? Timer A

Hi Amit,

Now the strange thing is I had it working for a short while yesterday, TM5A PWM pin CC0 with match count interrupt into vector after toggling the TASSMS bit (alternate mode select). One thing is the PWM configuration I originally had TIMER_CFG_A_PWM 0x0000.000A setting  bits TAMR and TACMAR where TIMER_TAMR_TAMR_PERIOD 0x0000.0002 only sets TAMR.

The basic configuration is very simple and does not disable the timer timeout interrupt TIMER_TAMR_TACINTD. So it seems the alternate mode select is somehow hampering the match set count and load set counts compare interrupts. When TAAMS is not set the match count interrupt should be free as default clear 0 enables capture and compare mode. Compare mode is match set count load!

The PWM configuration is touchy as it worked for a while cycling into the vector as the duty was changing, printf messages posting and then I messed inside the interrupt handler with the duty cycle code then it stopped on the next flash load. Perhaps you can get match count set interrupt to work as I did in periodic timer mode with PWM output on CC0 pin, but what was the WA and why did it work? TAAMS is set in this configuration but the default is capture compare mode.

 HWREG(TIMER5_BASE + TIMER_O_TAMR) = (TIMER_TAMR_TAMR_PERIOD | TIMER_TAMR_TAAMS | TIMER_TAMR_TAMIE);

 

Hello BP101

Which brings me back to the previous post. The Time Out and Time Match are not available in PWM Mode.

Regards
Amit

Hi Amit,

So why is this timer mode called PWM if the duty cycle can not be adjusted but only by direct calls to timer match set with update value changes. That method seems not of TI timers world.

The TAAMS(1) mode defaults to timer TO interrupt so in timer periodic mode there would be an NVIC interrupt, especially since TnPWMIE(0) is not set. Yet the RAW interrupt asserted is most always CnREIS or GPTM Timer A Capture Mode Event Raw Interrupt.

The timer is not set in edge capture mode rather TAAMS(1) mode, that mode sends PWM out the CC0 pin not into it in capture mode so the interrupt source would seem is being incorrectly set. The logic is sound.

 

Hi Amit,

I think you are confusing PWM alternate mode (out) with edge capture mode (in) different modes constrained by TAASM bit.

TAASM bit changes the timer mode CCx pin direction from edge capture (input) to PWM (output). That is why I broke down the registers to single bit set words to discover defects.

Hello BP101

Yes, I got confused as the 1st para was for PWM mode

Regards
Amit

Hi Amit,

It might just be timer 5A has this problem that timer TO will not assert or is disabled when TAASM(1) with a PWM signal is output on CC0.

The odd thing is the Timer 5A down count mode auto reloads when it reaches 0x0000 but won't assert an interrupt of any type. TMR5A is in periodic mode 0x0000.0002 and producing 25kHz PWM set in TAAMS(1).

My deduction is TAAMS(1) incorrectly disables all masked interrupts in periodic timer PWM output mode other than CAERIS "GPTM Timer A Capture Mode Event Raw Interrupt". CAERIS interrupt bit will not do anything with the timer load/set values or capture match events even when timer 5A is set for compare mode: {TIMER_TAMR_TCACT_M 0x0000E000 Timer Compare Action Select}. Seems setting the update mode TIMER_UP_MATCH_TIMEOUT somehow also masks the event capture interrupt when the timer is in capture mode TAMR(3). That might be correct but really don't know.

Hi Amit,

I found the problem is relative to when the timer is in 32 bit mode the PWM/Capture interrupts are asserted as expected however there no PWM signal (out) or capture (in) CCPx pins. Yet in 16 bit mode the vector interrupt fails for PWM yet works for capture mode. Found that out when switching to TMR4 and configured to do full wide PWM on a single pin.

It's only the (wide) timer which has 32 bit capability when in PWM Mode according to the MCU chart, below:

Might this explain?

Hello there CB1,

Agree 100%, point being made timers A/B interrupts are not working properly in edge count or PWM mode when 1/2 wide timer 16 bit mode is selected. A simple test is to put the timers in full wide and watch the interrupt clear repeat in cyclic manor. The TAAMS bit changes the direction of the CC0 pin IN or OUT so that doesn't appear suspect in the gating of interrupts logic.

Discovered  PWM interrupt CAREIS can not be cleared by TIMER_CAPA_MATCH or any other available INT clear method of a timer. Also Edge capture interrupt CBMRIS only sets one time, clears but wont retrigger on the next edge match after it has been cleared. However the edge match counter keeps counting up edges.

Perhaps Amit may know how to clear the CAREIS as not so clear even what NVIC interrupt number it holds.

 

Seems CCS5.4 debug was not telling the truth about clearing the edge capture interrupt triggering. Fact is it was occurring so fast after debug pause/resume it would only show 0 from that point on and 1 on pause. Planted USBprintf message confirmed it was actually rapidly interrupting and clearing.

Not the same truth for the CAREIS, then added a timer switch action for CC0 pin - TIMER_TAMR_TCACT_CLRTO but no help.

BP101 said:

watch the interrupt clear repeat in cyclic manor.

"Manor" properly describes poster Robert's English Tudor estate - which is far beyond your "Pb saturated yard" and cb1's back-room behind a back-room.

"Manner" may better describe such cycling...

Finally have  CAEI/CBEI interrupts TMRA set for PWM edge event interrupt and TMRB now set in edge time capture mode. Timer match set mode tends to lock up the edge count timer if the new count set value exceeds the value set GPTMTnILR. There is no GPTMTnMATCHR in edge time mode. So the timer is more resilient to get incoming edge times during the interrupt cycle since the counter reloads GPTMTbILR at the count set very low say 2-4 edges. 

The edge time mode example explains TnPWMIE interrupt source or at least attempts to connect the dots as to what TnPWMIE interrupt fires. That edge event source interrupt changes in edge count capture and match CHR to TnMIE. Hence the confusion why TnMIE does not exist in PWM edge event mode but does in edge capture mode. The outcome PWM edge event mode is we get an interrupt vector triggering at a very high rate of 25kHz versus the match CHR which uses far less interrupt time.

Some of the issue is also tied to the fan tachometer signal being open collector. That said the fan schematic shows pull up resistor required a10k to 3.3v. Oddly there is no taco signal out from fan unless PWM is input, appears fan derives taco from PWM input signal. From good practice added 100 ohms series resistor and 22k pull down which in hind sight 22k was pulling falling edges down to ground. Without the 22k taco floats 3v2 and falling edge never reaches below 1v6 when connect to the GPIO input pin.  

The CCP0/1 pin are both configured as inputs 2ma Standard.

Wonder if the open collector taco signal CCP1 input would be better configured OD so the 22k PD would not be required? The taco signal with 22k PD looks more like PWM in the center except for the rising and falling edges.