How to insert 1 clock delay after EPI read

Hi

I use the EPI in GP mode for FPGA interface 16 bit.

The FPGA interface need 1 EPI clock cycle as bus turn-over from read to write cycle.

This mean that after read cycle , the system will insert one EPI clock as turn over and then the write cycle will perform.

My configuration:

// valu of 4 = clock of 20Mhz
EPIDividerSet(EPI0_BASE, 4);

EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL);

EPIConfigGPModeSet(EPI0_BASE, EPI_FPGA_CONFIG, 8, 0);

EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_64KB | EPI_ADDR_RAM_BASE_6);

thanks