I ran into an issue flashing a factory-new TMP570LC4357A for the very first time. My debugger reported that it was unable to load its flash loader into SRAM. In a lower-level mode of the tools, I found that while I could connect to the target, alter execution, and change core registers, I could not write new values into the SRAM. It was as if it was write-protected somehow. The initial state of the SRAM seemed to be random (as expected on initial power-up), and the flash was not quite erased.
On a guess, I discovered that if I cleared the sram to zero using the MINITGCR and MSIENA registers, that flash erase and loading could proceed normally. My guess is that the SRAM's ECC was wrong, and therefore byte-wise or word-wise writes could not proceed. However, I could not find anything in the manuals to support my guess. On the contrary, the TRM suggests that double-bit errors are ignored on writes from the debug port.
So why couldn't SRAM writes work initially, and why does clearing the SRAM work around the problem?
