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[RM57L Launchpad] Questions regarding "etpwm_ecap_example"

honig
Intellectual 745 points
Other Parts Discussed in Thread: HALCOGEN

Dear community,

I have several questions regarding the "etpwm_ecap_example".

1. Under "PINMUX" tab after checking boxes "ETPWM" and "ECAP", ball A4 has a conflict. I removed ETPWM1SYNCI (synchronization of PWM to another input signal?), since the generated PWM in this tutorial should be considered as output. Must the synchronization of PWM signal refer to an external PWM signal or signals of other forms of waves? And since TBCLK sync (interal synchronization?) is enabled, ETPWM1SYNCI and ETPWM1SYNCO can both be disconnected?

2. Under "ETPWM1" tab in Clock Configuration, VCLK3 (MHz) the value 75.000 cannot be changed. Moreover HSPCLKDIV and CLKDIV are to be set to 0 according to the screen shot in the example, but the following codes mean that both of them should be set to 1.

/* Alternate code for configuring ETPWM and ECAP */
/* Set the TBCLK frequency = VCLK4 frequency = 90MHz */
etpwmSetClkDiv(etpwmREG1, ClkDiv_by_1, HspClkDiv_by_1);

Divided by 0 .. hmm doesn't make sense, so "set 0 (or 1) in GUI" mean "set 1 in the code"?

3. Under "ETPWM1" tab in PWM Configuration, there are two PWM (ETPWM xA and xB). Can I close either of them in the configuration?

I am an absolute beginner. Any tip or suggestion is highly appreciated!

Thanks in advance!

Best regards,
Honig

  • 0
    TI__Expert 4580 points
    Hello:

    I'll forward your question to HALCoGen team to provide some feedback.

    Regards,

    Enrique
  • 0 in reply to Enrique Lizarraga
    Intellectual 745 points
    Thank you Enrique!
  • 0 in reply to honig
    TI__Mastermind 32565 points

    Hello,

    1) This example needs only "ETPWM1A and ECAP1" pins to be enabled in the PINMUX tab. You can do it by manually enabling them in the tab or by checking the boxes ETPWM and ECAP (enables all EPWM and ECAP related pins) and remove the conflicts if any.

    ETPWMxSYNCI signals are used to synchronize the time-base counter with the counter of previous ePWM module instance. And EPWMxSYNCO signals are used to synchronize the counter of next ePWM module instance. ETPWMxSYNCI and EPWMxSYNCO signals are present for every module, but only EPWM1 signals are brought out to the pins. These are not needed for the normal functionality unless you need those pins to connected to some external hardware.

    The TBCLKSYNC allows users to globally synchronize all enabled ePWM modules to the time-base clock (TBCLK). When set, all enabled ePWM module clocks are started with the first rising edge of TBCLK aligned. This needs to be set for the clocks to be enabled.

    Please refer the device Technical Reference Manual for more details.

    2) In the GUI, it shows the CLKDIV and HSPCLKDIV prescale values. Prescale value 'n' means VCLK3 is divided by 'n-1'. There is typo in the comment provided in the example - It should be VCLK3 instead of VCLK4.

    3) No. You cannot disable any one of them. You can only disable at the module level which disables both A and B signals.

    Hope this helps!

    Thanks and Regards,

    Veena

  • 0 in reply to Veena Kamath
    Intellectual 745 points

    Hi Veena,

    >> 2) In the GUI, it shows the CLKDIV and HSPCLKDIV prescale values. Prescale value 'n' means VCLK3 is divided by 'n-1'. There is typo in the comment provided in the example - It should be VCLK3 instead of VCLK4.

    Q1: Typo "VCLK4" --> "VCLK3", hence in the example code "HL_sys_main.c":

    /* ECP notification */
void ecapNotification(ecapBASE_t *ecap, uint16 flags)
{
	uint32 cap1, cap2, cap3;
	float64 duty, period;

	cap1 = ecapGetCAP1(ecapREG2);
	cap2 = ecapGetCAP2(ecapREG2);
	cap3 = ecapGetCAP3(ecapREG2);

	duty   = (cap2 - cap1) * 1000 / VCLK4_FREQ; //VCLK4_FREQ --> VCLK3_FREQ ??
	period = (cap3 - cap1) * 1000 / VCLK4_FREQ;

	/* nanosec. to milisec. */
	duty *= 1.0/1000000;
	period *= 1.0/1000000;

	printf("Duty = %fms\n", duty);
	printf("Period = %fms\n\n", period);

}

    Q2: Prescale value 'n' means VCLK3 is divided by 'n-1'. I don't really understand this. If HSPCLKDIV=1, CLKDIV=128, then does it mean that:

    VCLK3(MHz) with a default value 75 MHz will be converted to 75 MHz / (128 -1) ? and divided by (1 - 1) ?

    Thanks in advance!

    Best regards,

    Honig

  • 0 in reply to honig
    TI__Mastermind 32565 points

    Hello,

    1) Yes. VCLK3_FREQ must be used instead of VCLK4_FREQ

    2) Sorry for the confusion. Its my mistake. I meant, to get a divider value of 'n', the prescale value must be set as 'n-1'. The GUI shows the prescaler values.

    TBCLK = VCLK3 / (HSPCLKDIV × CLKDIV)   where xxDIV value is prescale value + 1.

    Thanks and Regards,

    Veena