Disabling timer A interrupt source also disable timer B interrupt source - CCP0/1 split mode both timers capture mode

Hello BP101,

Please check that the IM bit for the timer that is still expected to work is set.

Regards
Amit

Hi Amit,

It was set but no interrupt when timer A interrupt source is disabled. Enable timer A interrupt and then timer B interrupt already enabled then starts asserting.

Unable to get a stable consistent edge time in edge timer mode so switched back over to edge capture mode. Edge time mode typical in QEI measure slower speeds under 1000 RPM so edge count seems a better choice to mimic QEI velocity timer behavior.

The cliff hanger about edge count mode is the timer is very strict about the TnILR value keeping a minimum of 2 edge counts above MatchCHR if ReSetting MatchCHR value in the interrupt cycle or the counter will not reload and interrupts stop asserting. That might be a good thing to add into the data sheet since most muffin fans now deliver 2 pulses per revolution, gives a good use for PWM and edge counts with CCP0/1.

Having a very difficult time reading the change in edge counts during interrupt time and calculating RPM as a much higher edge count speed than is reported. It seems there are 208 edges or 52 pulses per second at 6300 RPM. I believe the TnILR value has to be 2 times value of MatchCHR so the counter can count up to the maximum 208 edges per second. Seems If the spread between TnILR and MatchCHR  is not a multiple of 2 the timer will not reload when it reaches MatchCHR so jamming it with any value leads to unexpected timer mayhem. Does that sound about right?

Kindly provide make/model number/disty of your "muffin fan." We'll purchase one - and independently examine...

Hi CB1,

The fan is and ORION OD8032-24HBVXC10A. Will private connection details over to you.

The other thing for Amit is the data sheet makes a rather incorrect statement about TnMIE - GPTMnMATCHCHR interrupt only occurring in one shot and periodic modes. MatchCHR interrupt also occurs during edge capture mode as well. Some of the early confusion was result of missing information.

For taco speed It seems we must maintain 4 edges counted or 2 pulses but the frequency of the pulse time it takes to enter the interrupt can be derived from GPTMnBV 0x054 loaded into GPTMnBR 0x4c on the next timer cycle. It would seem the edge count should go up as the speed increases and that actually slows down the interrupt rate if the match value is allowed to increases. That approach seems counter intuitive in RPS/PPS unless the TnILR value is updated every interrupt cycle to relate the higher interrupt rate in edges captured. Yet the match count must seemingly sustain at 4 edges, 2 pulses / revolution or we loose our seconds basis in the conversion from RPS to RPM.  Very difficult to mimic an velocity timeout counter yet at this point it seems to work to some degree of relative math.

Hi Amit,

It occurred to me issue of when disable A PWM capture interrupt also disables B event capture interrupt may have to do with the fact both timers  were set  for TnPWMIE interrupt source. It seems timer B interrupt enable was being tied to timer A as if the timer was in 32 bit mode versus 16 bit.

That seemingly explains why I had so much trouble asserting MatchCHR interrupt in timer B in a PWM/Edge capture configuration with TnPWMIE set on both timers. Yellow is my find and addition. So in split mode only one timer can be set TnPWMIE enabled when the other 1/2 of timer is using the capture edge match interrupt when set to edge capture mode. 

5 TBMIE RW 0 GPTM Timer B Match Interrupt Enable

0        The match interrupt is disabled for match events. Additionally,  triggers to the DMA and ADC on match events are prevented.

1        An interrupt is generated when the match value in the  GPTMTBMATCHR register is reached in the one-shot, periodic modes and capture edge mode.

Hello BP101

But then why are you using the PWM in 32 bit mode!!!

Regards
Amit

Hi Amit,

Seems your missing the point that the original post using one TimerConfigure call for both timers A/B was incorrectly enabling TnPWMIE event interrupt for both timers. It wasn't until separating the configuration that an interrupt issue has been revealed and the register bit above post is missing an artifact. It seems that there are times when the 1/2 wide rule changes as when half the timer is in PWM mode and the other half is in edge capture count. In that case if TnPWMIE is enabled while in edge count mode with only half the timer it disables TnMIE even when it has been masked.

TimerConfigure should not automatically enable TnPWMIE in the configuration of 1/2 wide timers unless it has been explicitly passed in the ui32Config

Timers 5A/B split 1/2 width mode - PWM out and Edge capture will not assert either timer interrupt on match count..

 

    if(NEW_TIMER_CONFIGURATION)
    {
        HWREG(ui32Base + TIMER_O_TAMR) = (((ui32Config & 0x000f0000) >> 4) |
                                          (ui32Config & 0xff) |
                                          TIMER_TAMR_TAPWMIE);
        HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config & 0x00f00000) >> 8) |
                                          ((ui32Config >> 8) & 0xff) |
                                          TIMER_TBMR_TBPWMIE);

Hello BP101

So what you are saying is that using the half width timers with PWMIE bit set is causing an issue in Interrupt generation for Event Capture or Event Time mode?

Regards
Amit

Hi Amit,

Yes that seems to be the case and has causality when the timer is split half wide other then both set as PWM mode

Hello BP101,

OK. Let me investigate the same.

Regards
Amit

Hi Amit,

Oddly that same CCP1 input was damaged by letting the voltage float +3v4 when unconnected, MCU powered. Not sure how the input pin slowly shorted over 15 minutes, connected to CCP1 input the signal high dropped to 2v6 and later to 1v9 ending at 1v0. The maximum voltage for a fast GPIO pad is listed 4v in the electrical table 27-7. Seems 4v is not entirely true or it has some timer restraint. An other possibility; TimerConfigure somehow made the CCP1 pin an output direction timer B setting TAAMS in the shared 1/2 wide mode initial configuration. That seems unlikely to damage an input pin and most the time of this lab the input divider was 10k pull up +3v3 and 22k ground.

I only allowed 3v4 short while investigating another issue of the taco signal not being proper. Today discovered the open collector output of the fan has an undocumented minimum bias current. Goal was to stop any voltage or current feeding back into the GPIO when the 2v2 LDO was unpowered. Turns out my external resistor divider was limiting the current 94ua blow the minimum necessary to bias the open collector and made it float +3v4 on taco wire disconnected from CCP1 input. Made the voltage divider pull up current 355ua and all is well albeit on another timer CC0 pin. BTW there was no minimum listed for the open collector bias only the maximum was listed 5ma.