GPIO Input draws around 40mA when driven with 5V (TM4c123AE6PM)

Norbert Gassner said:

...unconnected inputs should be connected to GND with a 1kOhm resistor.   If we dont - what may happen?

If i may - it is never wise to allow an MCU input to "float."  (not be terminated)   As the inputs float randomly - current draw increases - and if these pins are (already) challenged that cannot be good.

The suggestion of adding a 1KΩ R to ground is bothersome - vendor rep here should advise as to why this method has replaced the more normal/customary method of employing the MCU's internal, weak pull-up/down Rs.  (such is a sure cost/space/labor saving)

If it's the GPIO "inputs" only which are plagued - perhaps shifting those unused MCU pins to outputs (set to your desired level) provides a better alternative...

cb1_mobile said:

surely has some basis. (I'd bet)

As would I.

I would also say

• It is wise to consider GPIO inputs since they will be until powered on. Yes I would put pull-up/dn on outputs as well to ensure a known state before the SW configures them
• I don't trust internal pull-ups, particularly since they are usually rather weak. However, since internal pull-up/dns are disabled until configured I'd also add external pull-up/dns on any inputs in any case (see don't trust). To be really effective the pull-up/dn has to be present at all times, otherwise you are accepting a risk of latchup until you 'get around' to initializing the GPIO. Consider what happens if reset is held for a long period. Note that latchup risk is not unique to this device, it is a common characteristic of all CMOS devices. They have become less susceptible to it as designs have improved but the risk is still present
• 1k does seem exceptionally strong and pull-dn seems unusual as well. The historical values have been 4k7 pull-ups and recently manufacturers have been suggesting 10k.
• SMT resistor arrays are small and inexpensive. Really the insurance (even if you use discrete resistors rather than arrays) costs you little.

I'm quite curious as to why a pull-dn rather than a pull-up, the margin is usually higher on the high side.

Robert

Amit Ashara said:

A fast rise and fall time trigger the ESD protection and causes the latch up. So it is required that the signal slope be increased so that the ESD is not triggered by a fast moving signal.   

Hi Amit,

Glad that you've responded - yet the response generates much concern.

Poster specified TM4C123AE6PM - is this GPIO "latch up" errata confined to that MCU, only?   (we doubt that)

We're long term users of past LX4F - and have regularly introduced "normal/customary" 3V3 level, external signals, into thousands of those MCUs - w/out noting this (unwanted) latch-up issue!   

May we ask the following:

• As we've long been told that "TM4C123 = LX4F" (in general) has our avoidance of this latch-up been "luck?" 
• Are all TM4C123x MCUs subject to this GPIO latch-up errata?
• Were the past LX4F MCUs subject to the same?   (such never appeared in LX4F errata)

Thanks much for your time & attention.

Yes - agreed - and (thus far) not well explained.

MCU vendors (most all) over-promote/promise w/"internal pull-up/down Rs" - and due to these internal's too high resistance they often prove ineffective. (just as you note)

Novice users - seeking to save "pennies" - condemn their (I2C most often + general GPIO) development to hours/days of (easily avoided) trouble-shooting - all prevented w/proper, external pull-up/down resistors...

Amit/Robert,

Thank you Amit - now the cure makes more sense.

Believe this vendor produces even beyond 4 channel "filter."

Even though posters Robert & cb1 demonstrate (some) activity here - both are "caught by surprise" by this (unfortunate) errata which is SO broad (and unwanted) in scope.

Hello Amit / All

For me a key issue is the 85°C which the errata says.

I see my problem at room temperature. So for me the important question is: "Is this statement is reliable?". If it is, the problem i see has another cause and i have to search further.

The question to all is: Does anyone else see this problem at RT?

We have a new design where we see the problem now and we have six or seven old designs, which go in low quantitys, where we need to replace the luminaries. One of them is still finnishred. If we need to add pulldowns to all unused pads our redesign cost (material cost isn't the issue) will blow up.

Regards Norbert 

Norbert, it also says high noise environments are more sensitive. (Only above 85C in "normal operating use" )

That's why I'm concerned, I consider our environment high noise (but noisy environment isn't explained either) but we probably don't get above 60C

Robert

Robert Adsett said:

The TM4C has higher tolerance when powered off IIRC.

OMG Robert - I too recall that (now) - yet was "lulled" into sleep-walk by vendor's (oft repeated) statement, "MCU's are identical - simply a Re-Brand/Paint Job!"

In our case - we try our best to "never/ever" allow signals to pass to our LX4F MCU board when board is unpowered...   (i.e. MCU "awakens" each/every external board - and powers them all down - (and checks) prior to the MCU's powering down...)

As an (independent) confirmation of Amit's writing (09:37, above) our firm has run GPIO tests on 10 TM4C123 devices, @ ±20°C beyond "normal" room temp. w/in our lab, and have not noted any ill effects...

cb1- said:

In our case - we try our best to "never/ever" allow signals to pass to our LX4F MCU board when board is unpowered...

I don't have the same external board setup as you but most of our inputs are in isolated power domains, the others do not have a path to the power rails. So it should have the same effect.

Norbert, any chance the micro is unpowered when this happens?  That would increase the chance of latching occurring I would expect.

Robert

Robert Adsett said:

badly routed pull-up on some I/O chips.

By badly routed - was the pull-up too far from the MCU's GPIO pin to be truly effective?