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System modules registers caching in TMS570 - MPU configuration

Piotr Roszak
Intellectual 530 points
Other Parts Discussed in Thread: TMS570LC4357, HALCOGEN

Hello,

I'm working with Hercules TMS570LC4357 MCU with standard Halcogen generated configuration for MPU.

It seems that I have problem with caching of some system registers, e.g. Flash Wrapper Registers (starting at 0xFFF87000U).
I observed that these registers are cached instead of 'write through', so the module behaves not as expected.

Halcogen configures this region of memory as DEVICE_NONSHAREABLE. Can this configuration be changed to any other (no cache or write through mode) with no side effects?

Piotr

  • 0
    TI__Guru**** 191736 points

    Hello Piotr,

      If the MPU region is declared DEVICE_NONSHARABLE then it is not cacheable. You seem to suggest that you are seeing a write-back caching type of behavior. What makes you say that? Can you please elaborate?  

  • 0 in reply to Charles Tsai
    Intellectual 530 points
    I want to check if Flash Bank 7 EEPROM sector is blank. What I do is:
    1) disable ECC for this sector using FEDACSDIS register;
    2) call Fapi_doBlankCheck
    3) enable ECC

    Despite ECC is disabled, I'm getting multiple ECC interrupts during execution of Fapi_doBlankCheck function. I am pretty sure that I assign FEDACSDIS with correct value - ECC interrupts do not occur in many other cases when I do the same sequence of instructions on erased memory. I also do not cross bank address boundary in function Fapi_doBlankCheck. So my impression was, that FEDACSDIS is sometimes not written back.

    Thanks,
    Piotr
  • 0 in reply to Piotr Roszak
    TI__Guru**** 191736 points

    Hi Piotr,

     Sorry I missed your reply until this morning. Can you try to set the EE_FEDACCTRL1.EOCV bit? By setting this bit, it allows the bank7 to have all '1' on both the data and ECC. The FEDACSDIS allows you to choose two sectors to disable ECC. But when you do blankcheck it might be checking the entire bank7 which consists of 32 sectors.

  • 0 in reply to Charles Tsai
    Intellectual 530 points

    I added setting of EE_FEDACCTRL1.EOCV bit and still the same issue. Could you provide me information which addresses of Flash Bank 7 are read exactly on TMS570LC4357 by Fapi_flushPipeline? I will also disable ECC for these sectors.

    Thanks,
    Piotr

  • 0 in reply to Piotr Roszak
    TI__Guru**** 191736 points

    Hi Piotr,

      Can you please send me your project so I can take a look?

      I don't think your problem has things to do with the pipeline buffer. What the flash wrapper has in the LC4357 device is the prefetch buffer. The logic tries to prefetch in advance the next sequential 32bytes of data before CPU requests it. You can try to disable the prefetch buffer by setting PFUENA and PFUENB bits in the FRDCNTRL register.