• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 30 subscribers
  • Views 389 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

There was an Interrupt in message box 18 when i sent the message by can bus, pls help me how to check it. Thanks a lot!

user4461578
Prodigy 170 points
Other Parts Discussed in Thread: HALCOGEN

I using 570 can bus send message. Message box configuration as following: No 18-32 for TX, polling send msg. When i send more than 30 message frames, There was an Interrupt in message box 18, and change the data in stack where is used to store the msg configure data. Send msg data code as following:

    for(i=0;i<ulFrameNum;i++)
    {
          ulMsgId = 0;
        ulMbId = canMESSAGE_BOX18+i%(canMESSAGE_BOX32-canMESSAGE_BOX17);
        while(canIsTxMessagePending(pCanReg, ulMbId))
        {
         }
        if(i==29)
        {
         }
        if((i>0)&&(i%15==0))
        {
            ulLstMbId = (i+15-1)%15+18;
             while(pCanReg->TXRQx[0] & 0xfffe0000)
            {
            }
        }
        ulMsgId |=((ulMsgType&0xF)<<24);
        ulMsgId |=((ulFrameNum&0xFF)<<8);
        if(i==ulFrameNum-1)
        {
            ulMsgId |= ulLstMacId;
            if(ulLen%DATA_FRAME_BYTE_NUM==0)
            {
                pstMsgObj[ulMbId].ui32MsgLen = DATA_FRAME_BYTE_NUM;
            }
            else
            {
                pstMsgObj[ulMbId].ui32MsgLen = ulLen%DATA_FRAME_BYTE_NUM;
            }
        }
        else
        {
            ulMsgId |= ulMidMacId;
            pstMsgObj[ulMbId].ui32MsgLen = DATA_FRAME_BYTE_NUM;
        }
        ulMsgId |= (i&0xFF);
        pstMsgObj[ulMbId].ui32MsgID = ulMsgId;
        pstMsgObj[ulMbId].pui8MsgData = pucDataTmp+i*DATA_FRAME_BYTE_NUM;
        CANMessageSet(pCanReg, ulMbId, &(pstMsgObj[ulMbId]), MSG_OBJ_TYPE_TX);
     }
The data in register and ram before msg 18 interrupted:


 

The data in register and ram after msg 18 interrupted:

  • 0
    TI__Guru**** 197386 points

    Hello,

    1. You need to enable the TX interrupt (high priority or low priority) for Message 18,

    2. Enable DCAN interrupt (DCAN0INT or DCAN1INT)

    3. Configure VIM to enable DCAN interrupt (channel 16 for CAN1 high, and channel 29 for CAN1 low)

    4. Set CAN interrupt to IRQ or FIQ

    Whenever the interrupt occurs, CPU will jump to ISR defined by yourself or by HALCoGen. I suggest you to use HALCoGen to generate the basic CAN driver which including the INT ISR, then you place your code to a function called notification.

    Regards,

    QJ

  • 0 in reply to QJ Wang
    Prodigy 170 points

    I have checked the problem. because of the SVC stack is too small (1024B), my code was over stack. Thank you for your reply.

    But I have another problem. I setup 1-16 message obj for FIFO receiving pkt, 17 for the last frame, the baudrate is 1M,

    i used the TM4C1294 for CAN receiver :

    when sent 35(more than 16) frames to this CAN IF, the No16 interrupt came in, i found that the data in msgbox 1--15 was right.

    The same as the data in 0--14 frame. But the data in msgbox 16 was not the same with frame 15, and the data in frame 34

    was in msgbox 16, the frame 35 data was in msgbox 17.   The phenomenon is the same as following(19.3.11.2 datasheet):

    To assure the correct function of a FIFO buffer, the CPU should
    read out the message objects starting with the message object with the lowest message number.
    When reading from the FIFO buffer, the user should be aware that a new received message is
    placed in the message object with the lowest message number for which the NEWDAT bit of the
    CANIFnMCTL register is clear. As a result, the order of the received messages in the FIFO is not
    guaranteed. Figure 19-3 on page 1365 shows how a set of message objects which are concatenated
    to a FIFO Buffer can be handled by the CPU.

    Can you help me what can i do next to fix it.  Thank you!