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Is GPIO high level 300na maximum input a requirement or restriction?

Genatco
Guru 56103 points


Hello world,

Some engineers are arguing the specification in the electrical section is vague at best but it seems may has merit under certain conditions.

Is 300na the maximum current required to get the input gate to bias into the on state at .68*VDD high level or the absolute maximum sink current in the input gate circuit?

Appears the output of a GPIO (2ma) connected to the input of another GPIO pin can short out the input gate over time even when high level current flow is less than 265ua. To insure 300na with only resistors it would require 100's of megohms series resistance between the coupled ports and cause a voltage drop across the resistor. If 300na is an input restriction that overly complicates customer circuit designs by requiring costly isolation circuits that run counter intuitive to the nature of what a GPIO port was designed to be. If a GPIO output can now produce over 12ma it should sink more than 300na configured as an input being that is logical deductive reasoning for most anyone who ever coupled a circuit to a PIO.

Without knowing how the input gate circuit is schematically configured, 300na maximum could have a different meaning among engineers. Especially true when some are convince current or (electrons) flows from + to - .Theory (not a hypothesis) science has confirmed electrons are current and flow from a lower into a higher potential (- to +). Holes are depleted electrons returning to the source potential to be replenished or reverse current in a silicon junction. How does the lowest potential of an electron get even lower or does it just spin in the opposite direction. It really doesn't matter but seems the 300na maximum high does when it should not.

  • 0
    TI__Guru**** 244440 points
    Hello BP101,

    It is the design spec for the current injected into the pad when in input mode when the Pin is seeing a logic High.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 56103 points
    Hi Amit,

    To me injection during a high level seems meaning less without a reference to the first stage of the input structure.
    Wouldn't current actually flow out of the GPIO input pin during a high level?
    How can current inject into the pin when the potential at the pin is above ground?

    I added a Schottky diode in series to stop any reverse current from flowing from GPIO input back to the GPIO output. Don't like the 310us roll off in the falling edge from the signal being output from the GPIO pin. My belief is we should be able to loop GPIO directly into input pins without any consequences when being forced by Tivaware to a 2ma level on all pin type settings. Looping digital outputs to digital inputs is a common practice without need of any external components.
  • 0 in reply to Genatco
    Guru 27665 points

    BP101 said:
    Wouldn't current actually flow out of the GPIO input pin during a high level?

    Why? The external potential is what is setting the level. The internal potential is high impedance and not driven, subject only to leakage.

    BP101 said:
    How can current inject into the pin when the potential at the pin is above ground?

    Best case with no leakage and high input impedance would be 0 amps.  I don't see how current could flow out w/o having a pull-up and the internal IC potential being above the external potential.

    BP101 said:
    My belief is we should be able to loop GPIO directly into input pins without any consequences

    Do you mean loop an output to an input? If so then yes (if they were TTL you'd want a pullup and that's still not a bad idea), likewise an input to an input (although you do need something to drive the inputs).  Output to output is not a good idea though.

    Robert

  • 0
    Guru 47900 points

    BP101 said:
    Appears the output of a GPIO (2ma) connected to the input of another GPIO pin can short out the input gate over time even when high level current flow is less than 265ua.

    And such apparition appears to whom?   When?   How often?   Upon how many boards?

    What cruel fate - outside of this sanitized report - (likely) befell that "tortured" input?   (and has been excised from this report.)

    I'd bet that rarely (likely never) have posters Robert, Amit & myself ever noted such, "shorting out of input gate over time!"  (w/out user mistake)

    Any such "appearance" is far more likely due to: "improper handling and/or operation - to include possible ESD effects" - and is highly unusual...

  • 0 in reply to Robert Adsett
    Guru 56103 points
    Hi Robert,
    >Best case with no leakage and high input impedance would be 0 amps. I don't see how current could flow out w/o having a pull-up and the internal IC potential being above the external potential

    Have to agree with most everything you have said. Yet the specification is injection current into the pin 300na maximum. So what if the current is actually flowing out of the input into an external pull up, what is the input pin reverse current maximum?

    So if a pull up resistor is set at 2v5 above the minimum high level formula (0.68*VDD = +2v2712 when VDD +3v34), how can current flow out the input?
    My guess is the internal LDO powers the GPIO at +2v2. That kind of explains injection currents going well beyond 300na are possible. Yet how do I know that for a fact other than by shorting out GPIO inputs and getting highly frustrated in the process.
  • 0 in reply to cb1
    Guru 27665 points

    cb1- said:
    BP101
    Appears the output of a GPIO (2ma) connected to the input of another GPIO pin can short out the input gate over time even when high level current flow is less than 265ua.

    Overlooked that. BP101 you do realize that 2mA drive means it is capable of 2mA, not that it must drive 2mA?

    Robert

  • 0 in reply to Genatco
    Guru 27665 points

    BP101 said:
    Have to agree with most everything you have said. Yet the specification is injection current into the pin 300na maximum. So what if the current is actually flowing out of the input into an external pull up,

    Under what possible circumstance is that going to happen with a pull-up?

    Robert

  • 0 in reply to Robert Adsett
    TI__Guru**** 244440 points
    Hello Robert

    Minimum guaranteed drive of 2mA

    Regards
    Amit
  • 0 in reply to Genatco
    Guru 27665 points

    BP101 said:
    So if a pull up resistor is set at 2v5 above the minimum high level formula (0.68*VDD = +2v2712 when VDD +3v34), how can current flow out the input?
    My guess is the internal LDO powers the GPIO at +2v2.

    What are you on about? That makes no sense whatsoever.

    Robert

  • 0 in reply to Amit Ashara
    Guru 27665 points
    That's pretty much what I said isn't it Amit? It can drive 2mA not that it must drive 2mA.

    IE if driving high and shorted to the high power rail it is not required to drive 2mA into the 3V3 supply.

    Robert
  • 0 in reply to Robert Adsett
    Guru 56103 points

    There is a -200uana maximum source current limit for GPIO input. The GPIO input at times floats at 1.25v from voltage derived of an GPIO output in the connected circuit. Do have a 4.7k pull down resistor on GPIO so 1.25v/4700=265ua has to be the pin killer when that condition occurs? Might have to up that value?

  • 0 in reply to Robert Adsett
    Guru 56103 points
    >What are you on about? That makes no sense whatsoever

    So we agree the LDO must not be powering the GPIO peripheral. Therefore internal Schottky protection diodes tied to the +VDD rail can not power the GPIO peripheral since those VDD pins are derived from a separate substrate not relative to the LDO rail.

    Have yet to witness in several tests placing +5v on a GPIO pin input ever it power the MCU via the GPIO pin protection diodes. I think it is safe to rule that pitfall of perhaps RA1 silicon was later corrected in RA2 i3 MCU.
  • 0 in reply to Genatco
    Guru 27665 points
    Are you wondering if a 4k7 pull down is going to destroy your input, then no. It's a high impedance input.

    However, if you have the pull-up enabled then it's min value is 13k and that forms a resistor divider with your pull-dn.

    Holding the input at an intermediate voltage (no matter how you do it) is likely to cause problems. But that has to do with problems other than the leakage current specifications.

    Robert
  • 0 in reply to Robert Adsett
    Guru 56103 points

    I would have to believe it depends on the output drive type and current capability into such a divider.

    This issue has multiple current paths. External circuit has an open collector output 4.7k PU to +5v and 4.7k PD setting input level into GPIO at 2v5. The GPIO 2ma output feeding the connected circuit back feeds into the GPIO input pin when the external circuit is not being powered. I don't think Its the GPIO output back feeding 1v25 a float voltage that 86 the GPIO input pin rather the injection current into the pin when the open collector current reversed as a result of the GPIO output 2v5 3v2. The injection current must be coming from either of the two 4.7k but witch one is the culprit or not at all?

    Above I was wrong stating -200ua and was actually -200na even worse.

  • 0 in reply to Genatco
    Guru 27665 points

    BP101 said:
    I would have to believe it depends on the output drive type and current capability into such a divider.

    Not very strongly, remember it's a high impedance input.

    The problem is that if your input is not in a defined high or low region then it will turn on both high and low FETs simultaneously. The resulting shoot through is fine if it is short but if left there then it will certainly heat up the input gate and may burn it out.  Worst case the entire IC goes into latch-up.

    BP101 said:
    External circuit has an open collector output 4.7k PU to +5v and 4.7k PD setting input level into GPIO at 2v5.

    Good heavens. Not much wonder you have a problem. Get rid of either the pull-up or pull-dn.

    BP101 said:
    The injection current must be coming from either of the two 4.7k but witch one is the culprit or not at all?

    Not at all, it's that resistor divider that's the issue.  You simply cannot have that.

    Robert

  • 0 in reply to Robert Adsett
    Guru 56103 points
    I think you ignore some facts an open collector requires a PU to even function and GPIO minimum input high level must be 0.68*VDD or 2.27v @3.34VDD. The circuit vendor claims TTL but to them +5v and they have an undocumented yet painfully discovered minimum bias current. So 10k PU disrupts the signal quality of the open collector, hence 4.7k PU.

    Now the odd part is even with PU 10k +3v3 PD 22k center tapped with 2.2k series the input still and eventually partially shorted. Another interesting part is a Schottky diode appears to have stabilized the timers CCP edge count reading. That seems to infer there is reverse current exiting the GPIO input configured default PAD as a push/pull HW pin. The Schottky cathode facing input has no measurable drop but expected would be at least .2v.
  • 0 in reply to Genatco
    Guru 56103 points

    BTW vendors circuit when floating unpowered, GPIO output back feed is at defined state of 1v25 a low at the GPIO input. This infers TI should investigate why GPIO input is behaving in this manor with an open collector transistor switch attached. Must be the first in history to connect TM4C 1294 GPIO into open collector NPN switch. Why we must isolate and design exotic coupler circuits with FET and resistors seems to me overkill when a GPIO can sink/source 12ma.

  • 0 in reply to Genatco
    Guru 10570 points
    Of course open collector requires a pull up. It is also not an input circuit and thus a non-sequitor.

    A resistor divider on an input that pulls the voltage to the indeterminate range will very likely cause a problem. If you have such you need to redesign whatever is driving your input.

    Robert

    Side note if you are driving an output high and it is being pulled low or vice versa that's also likely to cause problems but less certainly so and found different reasons
  • 0 in reply to Genatco
    Guru 10570 points
    If by floating unpowered you mean a floating input then the voltage is undefined. Leaving an input floating can result in the ic destroying itself. You must, absolutely must, have a pull up or pull down on every unused input. this has been true for decades.

    The ability of an output to drive 12ma is of no relevance to the behaviour of the input.

    Robert
  • 0 in reply to Robert Adsett72
    Guru 56103 points
    Think you have lost the point here that floating infers the unpowered connected circuit to the powered launch pad is receiving voltage from the GPIO output port and back feeding it through open collector into the GPIO input. Common ground defines the float voltage +1v25 a low to the GPIO input. These are not non powered pins in this GPIO connection. Yet how to measure open collector current flow as 12000 count DVM is pricey. Better yet to limit GPIO input sink current under -200na would take several 100 megohms. Sink in belief the undesired -200na current is flowing from the GPIO input back to the GPIO output. Indeed exotic buffers outside the TTL buffers would be required to stop this current flow anomaly.

    Obvious in my view - the voltage is not the issue rather current flow where logic low has -200na max. Since 1v25 falls below a defined logic high that rules out 300na. The foot note (a) in table 27-7 makes me wonder if the input MUX is being programmed correctly. (a. Output/pull-up/pull-down disabled; only input enabled). It seems the Tiva function programs CPP pintype appears correct (no PD) but the ROM matrix may not be set correctly. How could anyone know since the MUX values are coded and no table exists to decode the matrix. The GPIO input edge/count captures slip away from the timer like melting butter and appear as random misses in debug at 100ms refresh rate printing out count values exactly the same.
  • 0 in reply to Genatco
    Guru 27665 points

    BP101 said:
    floating infers the unpowered connected circuit to the powered launch pad is receiving voltage

    That's a rather individual definition of a floating input. Pretty much the exact opposite of the definition used by everyone else.

    BP101 said:
    Obvious in my view - the voltage is not the issue rather current flow where logic low has -200na max.

    You may find it obvious. It is however completely and utterly wrong.

    BP101 said:
    The GPIO input edge/count captures slip away from the timer like melting butter and appear as random misses in debug at 100ms refresh rate printing out count values exactly the same.

    Hardly surprising given what you've told us so far.

    Robert

  • 0 in reply to Robert Adsett
    Guru 56103 points
    Robert Floating in the context that term was used. From the view of the non-powered circuit the voltage is floating and not clearly defined as when the power is applied to the remote circuit.

    >"You may find it obvious. It is however completely and utterly wrong"
    So you have previously described the input as being a high impedance source. Yet it clearly has restrictions on the amount of series current in both directions at both high an low logic levels. How that current restriction is being abused lies at the heart of the input topology which we have access denied. That said, you are making assumptions about the input design using terms hot and shoot through to describe the current restrictions. I tend to think it should be source current leaving the input at 1v25 pin making way back to the output and argued a point the open collector current reverses when the power is applied to the remote circuit. You have yet to made an argument to convince me how that can simply be ruled out. If the remote circuit is first powered before the launch pad is powered the logic level at the GPIO input is 2v58 at 100Hz frequency and a nice square wave riding zero vector, TTL level. How much more does a TTL buffered input need to have a TTL signal than it already does. That is unless the TTL input buffer is bugged.

    The ideal answer would be to include the TI current restrictions in describing what is pushing those limits by using ohms law. You have not yet provided any proof in formula notation that makes your claim of voltage divider valid. I on the other had have stated the 4.7k PD at 1.25v presents a current of 265ua to ground, if of course current is flowing out of the input under certain conditions. What those conditions are need to be discovered or even derailed for the more likely scenario. The Schottky diode will perhaps be the soothsayer in a week gone by with out having a shorted pin. To me 265ua goes so far beyond -200na its laughable.
  • 0 in reply to Genatco
    Guru 27665 points

    BP101 said:
    Robert Floating in the context that term was used. From the view of the non-powered circuit the voltage is floating and not clearly defined as when the power is applied to the remote circuit.

    Like I said, that is a unique and personal definition. Most would consider it wrong. Certainly it impedes communication with those expecting the usual definition.

    BP101 said:
    So you have previously described the input as being a high impedance source.

    No I defined it as a high impedance input. It is not a source.

    BP101 said:
    Yet it clearly has restrictions on the amount of series current in both directions at both high an low logic levels.

    It is an imperfect input, it has leaks. Parasitics that provide a limit on how small your drive can be to maintain a level.

    BP101 said:
    I tend to think it should be source current leaving the input at 1v25 pin

    You may think that, it doesn't make it right. It is, in fact quite wrong.

    BP101 said:
    That is unless the TTL input buffer is bugged.

    Your input circuit is wrong. You could provide a sketch but to the extent that your description is accurate it is clear your input circuit is wrong.

    BP101 said:
    You have not yet provided any proof in formula notation that makes your claim of voltage divider valid.

    You have a pull-up and a pull-dn on the same input, that is by definition a divider.

    Robert

  • 0 in reply to Robert Adsett
    Guru 56103 points
    > You have a pull-up and a pull-dn on the same input, that is by definition a divider.

    Again how is that violating TI input topology current limits? Besides to keep stating it is wrong suggest how that violates input current restrictions. Otherwise your argument is merely conjecture!

    Simply keep saying it's wrong is not very convincing when the signal is at TI 3v3 TTL level.
  • 0 in reply to Genatco
    Guru 27665 points

    BP101 said:
    Again how is that violating TI input topology current limits?

    It violates the voltage requirements. Not just with TI either, every manufacturer of logic has the same limitations.

    BP101 said:
    suggest how that violates input current restrictions.

    I've never said it does. I have said it violates the voltage level requirements.

    BP101 said:
    Simply keep saying it's wrong is not very convincing when the signal is at TI 3v3 TTL level.

    That is at odds with what you have been saying for the previous several pages. Maybe you just haven't communicated it clearly.

    Robert

    You might try a circuit sketch. I expect no one other than yourself has any idea what your circuit looks like at this point.

  • 0 in reply to Robert Adsett
    Guru 56103 points

    Again 1v25 is above what TM4C1294 defines as a recommended low logic level in data sheet. The recommended logic high minimum is defined 0.68*VDD=2v27v <= 4v0 maximum. Input voltage level below 2v27 fall below the recommend low but is not a restriction.

    The maximum recommended low level is 0.35*VDD=1v169 >= 0v0 minimum. 

    Relative to those numbers 1v25 is above 1v169 and below 2v27 safe area and will do not harm the input as it is not considered a restriction. Have recently had GPIO more than one inputs react with a high level low as 1v9 when presented with a slow slew rate.

     Recommend is not a restriction by definition of the word. So 1v25 seems to fall into the low level category not yet quite a high.

  • 0 in reply to Robert Adsett
    Guru 47900 points

    Sometimes - might, "Strength in numbers" comfort & guide?

    My small tech firm has designed, built, tested & shipped several thousand ARM MCU-based boards during CY2015.   Small firms must find their tech & market, "niche" - steer that to clients' areas of interest - and then - as best as they're able - design w/in normal/customary convention.

    In that process - we make it our business to carefully examine - and model - the design & production efforts of the market & tech leaders.  (while adding our unique, "magic" brew)   And in this process - NEVER have we noted the use of "Pull-up AND Pull-down" resistors - attached to MCU pins - "known" to be inputs!   My firm has easily reviewed 100 product schematics of "others" (all leaders) that use of (both) pull-up and pull-down is not in evidence!   Note too that this MCU vendor - and many others - often allow the option of Pull-up OR Pull-down - but NEVER have we noted (both) options to be simultaneously allowed!

    Further - most engineers at our firm - and the giants we're fortunate to contract with - focus upon insuring that the input Voltage Levels - fed to MCU inputs - are proper.   Little (sometimes no) thought is given to current flow into or out from such MCU input pins.   Focus upon our Amit - who many times each day (likely) must connect a GPIO Output to a GPIO Input.    Do you believe that each/every time (only carefully & after great consideration)  - he makes that connection?  (and only after he employs pull-up AND pull-down AND Schottky diode - to each/every input pin!)  (I do not - nor should you - so long as the correct signal level is provided - all should be well!)

    The lesson then, "So long as the correct input voltage is provided - such MCU input currents are well-behaved, well-bounded."

    You arrived at this "near obsession w/MCU input currents" most likely after experiencing MCU GPIO pin issues.  (perhaps caused by your "unique" pull up AND down (together) additions!) 

    Your designs are (always) prototypes - often in very high flux - and thus the "quest for answers" may have led you into "unproductive" (input current) territory.

    If you can confine input signal voltage levels to MCU specified levels - either comfortably low or high (i.e. w/adequate signal margins)  - the intense interest in input currents may subside.

    Many here want you to succeed.   Culling yourself - so far from the mainstream - may not prove best/brightest ...  (at some point - even Lone Ranger must Ship!)

  • 0 in reply to cb1
    Guru 56103 points

    Kirk unit - Veyager must evolve!

    Noting it did evolve.

  • 0 in reply to Robert Adsett
    Guru 56103 points
    Hi Robert,

    Think I may have caused you/me confusion in describing the GPIO output was feeding back to the GPIO input via the unpowered circuit when that condition was systemic. Now aware +1v25 level was from the shorted pin pulling down the pull up tied to +5. Recently switched from +3v3 to +5v0 PU after discovering 10k pull up would not produce enough bias current to drive the open collector. Note that PU change +5v was at the instruction of a 3rd party vendor which BTW other circuit feeds via +24v power supply. Hence my apprehension at removing the pull down divider and later Schottky diode addition after seeing the input level rise to +3v4 an short the input. We used to terminate TTL level devices placed at the end of long ribbon cables in just this way.

    Long story short the pin has survived may cycles of what sees to have been reverse current leaving the input. Now have 4.7k PU to +3v3 and 22k pull down terminating the input at 2v75, noting the oscilloscope signal level is true and DVM lies. Not sure what made the input rise to +3v4 when the PU was at +5v or +3v3. Each time input voltage rose to +3v4 (well in specification); the first pin tested slowly shorted out over days and the next one same day. So far all is well after the addition of the Schottky diode at the input no matter each boards power up sequence.

    Interestingly just had an LM7005 switcher blow the top at the input pin. IC input is good to 80v Max yet the pin voltage remains nominal at +33v unregulated from a toroidal linear power supply. Toroid supply had been switched on many times without any such havoc but this time the 20 amp panel breaker tripped as it sometimes does with a 2Kw supply. The LM circuit power pin originally had a Schottky diode (removed) mainly to stop polarity reversal, or so I thought. From past engineers note book (Forest Mims 3rd) recall a series diode also stops reverse current (holes) from destroying an IC's VCC substrate. Have never added such a series diode with NMOS or PMOS devices in the past but after seeing the LM blow the edge of plastic case right at the power input pin. Tend to support other reasons for a Schottky series diode. Now considering even adding a series resistor after seeing the inrush reverse surge do this to an 80v input. Tend to believe there are no holes at all rather electrons spinning in a CCKW direction making way back to B+.