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Timer ALTCLK source bit is not clearing on configured timers.

Genatco
Guru 56143 points


Hello forum,

For some reason it seems the ALTCLK source bit is not clearing when set for SYSTEM_CLOCK and the timers default to PIOSC_CLOCK 16Mhz. The times debug checked timer PP register 27 bit 6 was set ALTCLK has explicitly asserted PIOSC in the configuration. So I was oblivious the it never set 120Mhz timer clocks. 

Now aware all my configured timers never cleared bit 6 in register 27 when explicitly configured to do so.

TM4C1296NCPDTi3

This command does not work:

ROM_TimerClockSourceSet(TIMER1_BASE, TIMER_CLOCK_SYSTEM);

  • 0
    TI__Guru**** 244440 points
    Hello BP101,

    The API affects the function of the register GPTMCC and not GPTMPP. GPTMPP is RO

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 56143 points
    Hi Amit,

    Exactly my point the timers clock source is always set PIOSC when it has been configured for SYSTEM. That explains abnormally slow edge counts 1/5 or less the actual edge count speed and perhaps many other odd behavior in the divisor used for several other periodic timers.

    The ALTCLK source bit 6 is never clear inferring to me the timer block never switched to SYSTEM 120Mhz clock. So it seems as if all timers are PIOSC 16Mhz even after setting the clock to use 120Mhz SYSTEM. Why have a ALTCLK source RO if it doesn't matter being shouldn't it change from 1 to 0 after setting PIOS in GPTMCC? If that is not the case then the timer block divisor is set wrong somewhere in MOS clock?
  • 0 in reply to Genatco
    TI__Guru**** 244440 points
    Hello BP101

    The GPTMPP register is indicative of feature available. Having the bit set to 1 would mean that the PIOSC may be used by setting the bit in GPTMCC register.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 56143 points
    Hi Amit,
    The problem was the timer does not count 2 edges at the correct frequency in up count mode, best achievable is 1/2 the frequency. Switching the timer to down count resolves the frequency issues of up direction edge counts timer mode and likely the edge time mode.