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ADC Input readings propagate between channels on RM46

Other Parts Discussed in Thread: HALCOGEN, TINA-TI

Hey everyone,


I am using the ADC modules on a RM46 to sample a few analog inputs. These are custom PCBs and I have attached the important parts of the electrical schematic. The issue I am seeing is a small cross over between ADC channels in the same group that is proportional to and input channel. For example the figure below is a capture of AIN[2], AIN[3] and AREFHI pins to the RM46L852-PGET chip. When I increase the voltage going into AIN[2] you can see an increase in the noise on AIN[3]. This translates into readings crossing the channel. With AIN[2] at ~0 AIN[3] is ~0 but when I increase AIN[2] to ~3600 AIN[3] increases to ~316. BUT this does not work in reverse, increasing the input into AIN[3] does not effect AIN[2] like I would expect:

After some debugging I found that the noise corresponds to my ADC samples:


There are breaks visible when the CPU is not doing ADC conversions, like writing to CAN or SCI. In my software I am running this:

void main()
{
    	adcInit();

    	while(1)
    	{
    	    	adcData_t d[ADC_MAX_CHANNEL_COUNT];

	    	adcStartConversion( adcREG1, adcGROUP1 );
	    	// wait while ADC is converting
	    	while( !adcIsConversionComplete( adcREG1, adcGROUP1 ) );
	    	// Get the data
	    	adcGetData( adcREG1, adcGROUP1, &d[0]);

	    	brakePressureMonitor.Raw = d[0].value;
	    	tsVehicleVoltageMonitor.Raw = d[1].value;
	    	driveThrottleOneMonitor.Raw = d[2].value;
	    	driveThrottleTwoMonitor.Raw = d[3].value;

    	    	// Other stuff afterwords eg. CAN transmissions, SCI transmissions
    	}
}

Schematics:

Any ideas what could be causing this behavior? If you would like any more information let me know!

Thanks,

Nathan

  • Nathan,

    Since the ADC inputs all are switched into the same Sample & Hold - which is basically a big cap - it's going to be normal to have some charge sharing when the switches occur.
    There is a mode of the ADC where you can completely discharge this cap between conversions if that would help. But otherwise, are the inputs that are having this trouble buffered like your DR_THROTTLE inputs in the figure above?
  • Humm, makes sense. I'll try changing that in HalCoGen and seeing if that helps.

    Yes, Basically an analog voltage from a potentiometer comes in as a 0-5V signal and is scaled down to 0-3.3V using the OpAmp circuits. Those outputs are fed into the ADC inputs then.

    I am seeing the issue like a ladder down those inputs. Eg. AD1IN[0] effects AD1IN[1], AD1IN[1] effects AD1IN[2], AD1IN[2] effects AD1IN[3], and AD1IN[3] effects AD1IN[0]. Is there a way I can sample each channel separately to reduce the propagation?

    Thanks,
    Nathan
  • The "discharge capacitor" option definitely made my input a LOT more stable, but I am still seeing the cross of the channels. Any other ideas?
  • The ladder makes sense because in the default mode, the ADC processes the channels in linear order. So the previous state of the sampling cap when ADIN[2] is sampled would be dependent on ADIN[1], but ADIN[1] would not be dependent on ADIN[2].

    There is a way to change the sampling order, but I'm not sure that it's the best bet in this case. Since your inputs are all buffered, probably just increase the sample time to allow enough time for the input to settle to within whatever accuracy you need it to.

    There is an equivalent circuit model of the ADC switches and sample cap in the datasheet for the device, if you take this into a tool like Tina TI and include your opamp, you should be able to reproduce what you see on the bench.
  • Are you actually seeing the cross of the channels with the discharge cap option? I would expect more that you would always see a 'dip' on the channels as they start to charge-share w. the discharged sampling cap.
  • Here are my ADC settings:

    And I am seeing the identical output, but at a smaller peak to peak voltage:

  • Got it! I set the discharge time to ~1000ns and everything works now! Is there a way to calculate what that value should be?

    Thanks for the help!
  • Hi Nathan,

    Yes absolutely.

    That is what the equivalent circuit in the datasheet is for.
    I would probably model this in Tina-TI and watch for the settling time in response to a unit step input through your driver circuit. You want to settle to within < 1/2 LSB of the ADC step size so < 0.8mV.of the final value. I would probably start with the capacitors inside the ADC discharged.

    I think though you should be fine close to 200ns of sampling time however I cannot tell for sure because I don't know what the buffers on the other drivers look like.
  • Awesome! Thank you for the guidance. These forums are awesome!

    Nathan
  • You can also refer to this app note:

  • Just a quick question.

    Are you using your Saleae app with their USB analyser to graph these waveforms or are you loading data directly into the app for viewing?

    I ask because we've found some crosstalk on our Saleae analysers which produces similar results when monitoring adjacent channels.

    Cheers.

  • I am using a Logic Pro8 for at ~1.6MHz for the capture. I haven't seen any major cross talk issues with our analyzer.

    Saleae has been extremely helpful for us, an email to them wouldn't hurt.

    Hope this helps,

    Nathan

  • We emailed them about a problem we had with a iLogic showing cross-talk. They were very helpful and responsive!.

    I just wanted to put it out there as a possible source of error in your measurements, that's all.

    Cheers.