Error in Halcogen? PLL Control register1

Akshay Immanuel

Other Parts Discussed in Thread: HALCOGEN

While configuring my PLL settings to 330Mhz as shown in the diagram.

My PostODClk is required to be VCO Clk/1.

Page 163,Table 2-44 PLL Control Register 1 - Bit 28-24 states that to obtain a division by 1,we must load value 0 in bits 28-24.

The halcogen generated code however is loading 0x1F to those bit positions.

What is missing here?

Why is it dividing by 32 when i have selected divide by 1 in my GUI of halcogen?

over 10 years ago

0 Anthony F. Seely over 10 years ago

TI__Guru 69070 points

Hi Akshay,

The function mapClocks() changes the initial value of the divider (0xF) ... the largest divider ... to the value you select in HalCoGen. But it does this after the PLL is locked. So it's a 2 step process.

You should see your selected value appear in the write to PLLCTL1 in mapClocks().

-Anthony

0 Akshay Immanuel over 10 years ago in reply to Anthony F. Seely

Expert 1160 points

My Bad sorry :)

0 Anthony F. Seely over 10 years ago in reply to Akshay Immanuel

TI__Guru 69070 points

No Akshay - not your bad - we really appreciate questions like this; more often than not there is a real issue and without targeted feedback we can't improve. Honestly I was worried that there was an issue until I researched it. I wound up using Notepad++ to do a directory search to check to see if PLLCTL1 was written elsewhere - that's the only way I found the 2nd write. Then it all made sense.

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Error in Halcogen? PLL Control register1