We are using LM3S9B96-IQC80-A2
We are shipping hardware in a series application.
hardware with LM3S9B96 is used on various pcb's.
All pcb versions have JTAG/SWD connector.
Production flash loading is not an issue.
We want to do flash verification and, if necessary, flash
re-programming under supversion of an additional CPU,
hooked to SWD on the debug connector.
We know and comprehend ARM's "ARM Debug Interface Architecture Specification".
We know and comprehend TI's "LM3S9D96 Microcontroller DATA SHEET"
We know how to handle on chip Flash of Stellaris LM3S (we've written our own boot loader).
Currently, we are implementing SWD access to Stellaris's SWD-AP.
Once we inside SWD-AP, we want to use MEM-AP to access all
memory mapped ressourecs to do the job.
Q1: where do we find a reference of SWD-AP and MEM-AP registers?
Q2: is the result of a MEM-AP driven access EXCACLTY the same
as a memory access done by the running Stellaris CPU?
Q3: With reference to Q2, do I have to consider any specialities
when reading and programming flash memory through SWD-AP / MEM-AP?
Q4: Can you direct me to any TI appnote doing the above job?
(similar to SILICON LABS's AN0062)
Maybe you have a similar solition in one of the vintage
Stellaris EVA boards?
Please, do NOT advice to use 3rd party programming/debug tools.
Our solution has to run on a small embedded CPU (Cortex-M3)
doing SWD by directly manipulating port pins.
Please, do NOT advice to migrate to the next evolution of CPUs (TM4C).
We are already in the process of doint it. But for the time being,
we MUST keep on producing our current hardware. And we MUST increase
the reliability level of onboard flash.
Thanks
