We are getting some returns from the field. I started to question whether the SPI traffic was working. I grabbed some traces and found that sporadically the SPI clock seems to fail to transition low. The circuit does not have any pull up or pull down resisters on any of the lines.
I find nothing in the errata for this chip about the serial clock. I did not get any hits searching e2e.
I cannot explain why the transfers work > 99.5% of the time.
Is there experience of the SPI clock not transitioning?
The code that generates the following is included below.
WRLS_MRF_CS_Enable();
// Send the command
ROM_SSIDataPut(SSI0_BASE, (UINT32) (((address >> 3) & 0x7F) | 0x80));
ROM_SSIDataPut(SSI0_BASE, (UINT32) (((address << 5) & 0xE0)));
while(ROM_SSIBusy(SSI0_BASE)); // Spin
// Empty FIFO incase there is something in there
while(ROM_SSIDataGetNonBlocking(SSI0_BASE, &temp))
{
// Spin until there is no more data to read.
}
// Drive the clock
ROM_SSIDataPut(SSI0_BASE, 0x00); // Provide the clock
while(ROM_SSIBusy(SSI0_BASE)); // Spin
// Read the FIFO
ROM_SSIDataGet(SSI0_BASE, &temp);
toReturn = (SINT8) temp;
WRLS_MRF_CS_Disable();
