Problem in Coincident sampling mode for both ADC

Dhiman Das

Hi!
I want to sample both ADC0 and ADC1 module simultaneously, from PE3 (AIN0) and PE2(AIN1) with hardware averaging but after writing the following code only PE2 is and I get same value from both ADC0 and ADC1. Please check where my configuration is wrong,

#include <stdint.h>
#include <stdbool.h>
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_gpio.h"
#include "inc/hw_adc.h"
#include "driverlib/sysctl.h"
#include "driverlib/pin_map.h"
#include "driverlib/rom_map.h"
#include "driverlib/gpio.h"
#include "driverlib/adc.h"

#ifdef DEBUG
void
__error__(char *pcFilename, unsigned long ulLine)
{
}
#endif


int main(void)
{
unsigned long ulV_ADC_0=0,v=0;
unsigned long ulI_ADC_1=0,i=0;

SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_OSC_MAIN|SYSCTL_XTAL_16MHZ); // 40MHz

//
// Enable Peripheral Clocks
//
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);

//
// Enable pin PE2 for ADC AIN1
//
MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_2);

//
// Enable pin PE3 for ADC AIN0
//
MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_3);

SysCtlADCSpeedSet(SYSCTL_ADCSPEED_1MSPS); // Set Speed for both ADC
ADCSequenceDisable(ADC0_BASE|ADC1_BASE, 3);

ADCPhaseDelaySet(ADC0_BASE|ADC1_BASE,ADC_PHASE_0);

ADCSequenceStepConfigure(ADC0_BASE|ADC1_BASE, 3, 0, ADC_CTL_CH0|ADC_CTL_CH1 | ADC_CTL_IE |ADC_CTL_END);

ADCSequenceEnable(ADC0_BASE|ADC1_BASE, 3);

while(1)
{
ADCIntClear(ADC0_BASE|ADC1_BASE, 3);
ADCProcessorTrigger(ADC0_BASE, 3);
while(!ADCIntStatus(ADC0_BASE, 3, false))
{
}
ADCSequenceDataGet(ADC0_BASE, 3, &ulV_ADC_0);
ADCProcessorTrigger(ADC1_BASE, 3);
while(!ADCIntStatus(ADC1_BASE, 3, false))
{
}
ADCSequenceDataGet(ADC1_BASE, 3, &ulI_ADC_1);
v=ulV_ADC_0;
i=ulI_ADC_1;
}
}

over 10 years ago

0 Amit Ashara over 10 years ago

TI__Guru**** 244400 points

Hello Dhiman,

"ADC0_BASE|ADC1_BASE" is not a valid operation. For each ADC the setup has to be done separately.

Regards
Amit

0 Dhiman Das over 10 years ago in reply to Amit Ashara

Intellectual 270 points

What about the function ADCPhaseDelaySet() according to the datasheet there is no ADC0_BASE or ADC1_BASE.

0 Amit Ashara over 10 years ago in reply to Dhiman Das

TI__Guru**** 244400 points

Hello Dhiman,

I understood from the first post that the two channels need to be sample at the same time. In that case you do not need to set the phase delay. Instead use the Global Synchronization so that triggering one ADC will start both the ADCs to sample.

However do note that since the Sync has to cross clock domains, there may be 0-3 sampling clock cycle delays in the actual samples

Regards
Amit

0 Dhiman Das over 10 years ago in reply to Amit Ashara

Intellectual 270 points

Hello Amit
Thanks! it works. How could I able to know that the both adcs are sampled the data simultaneously?

0 Amit Ashara over 10 years ago in reply to Dhiman Das

TI__Guru**** 244400 points

Hello Dhiman,

I guess our posts crossed at the same time. Do note that while the Phase Delay can be used to align the edges, it may change from device to device.

Regards
Amit

0 Dhiman Das over 10 years ago in reply to Amit Ashara

Intellectual 270 points

Hello Amit,
Thanks again. Would please suggest how to use Global Synchronization in CSS.

0 Amit Ashara over 10 years ago in reply to Dhiman Das

TI__Guru**** 244400 points

Hello Dhiman,

Configure the ADC using ADCProcessorTrigger with the parameter of ADC_TRIGGER_WAIT.

ADCProcessorTrigger(ADC0_BASE,ADC_TRIGGER_WAIT | 0x3);
ADCProcessorTrigger(ADC1_BASE,ADC_TRIGGER_WAIT | 0x3);

When you need to perform the conversion, set the ADC_PSSI register bit 31. There is no API to do the second step and has to be done with HWREG macro call.

Regards
Amit

Arm-based microcontrollers

Arm-based microcontrollers forum

Problem in Coincident sampling mode for both ADC