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Tiva TM4C129 SSI Slave Issue

Alan Neidig
Intellectual 255 points

Other Parts Discussed in Thread: TM4C1292NCPDT

We are having a very difficult time getting Tiva SSI slave functionality working.   

 

SSI slave Tiva:  TM4C1292NCPDT

SSI master: Nordic nRF51822

 

Our baseline design has NO pull up/pull downs on the lines between the two devices, just traces.

 

Our Tiva development environment:

TI-RTOS: 2.10.01.38

CCS: v6

We are using the Freescale/Motorola format.  The Slave Select (SS) line is pulled low during the entire transfer.  We are using mode 0 (CPHA=0 and CPOL=0).   We are configuring it to use SSI3.  The Tiva pins we are using are:

 

PF0 - MOSI

PF1 - MISO

PF2 - SS

PF3 - SCLK

 

We have already confirmed that the master is sending the SPI data in the correct format.  We did this on a separate Nordic development board and monitored the traffic using a SPI bus analyzer.   All data looks perfect.

 

The issue we are seeing is that the Slave Select line from the nRF to the Tiva goes low very slowly.   It will eventually get to the ground threshold, but it takes so long that the SSI tranfer is completed before the line ever gets to ground.   We tried enabling the internal pull down resistor on the Slave Select pin, but that didn't work.  

We then put an external 10k pull down on the line and the line was able to to start functioning properly.   However, we we re-programmed the Tiva with the latest code using the settings below, the SS line quit toggling completely.   It always stays low.

 

We believe one of two things happend:

1) Something changed in the Tiva configuration from what we had when it was working

2) We blew up the Slave Select port on the No​rdic nRF or Tiva

 

Before we test on a second board (possibly damaging it), can you give us some feedback/suggestions?

 

Are these the correct Tiva register settings?

If the SSI3 alternate functionality is enabled, will the internal pullup/pulldown function or must an external resistor be added?

There shouldn't be an issue, but can you confirm that adding an external pull down resistor on the Slave Select line is OK?

 

Any other feedback on Tiva SSI slave functionality would be welcomed.

 

We have also reviewed the errata and only SSI#06 (SSI Receive FIFO Time-out Interrupt may Assert Sooner than Expected in Slave Mode) would seem to relate to our setup, but is not the issue we are currently seeing.

 

 

 

 

Below are the current Tiva SSI3 port settings.

 

 

 

Thanks in advance,

Alan 

  • 0
    TI__Guru**** 244440 points
    Hello Alan

    The images are missing in your post

    Regards
    Amit
  • 0
    Intellectual 255 points
    Amit,
     
    Thank you very much for the quick reply.
     
    Once you have had a chance to review, we would like to have a quick call to discuss.  Hopefully, this is something simple and quick.
     
    Here is the scope shot.
     
     
     
    Here are the register settings …
     
     
     
     
    Thanks in advance,
    Alan Neidig
    Sr. Field Applications Engineer
    Arrow Electronics
    11500 Metric Blvd.
    Suite 300
    Austin, TX 78758
     
    W: (512) 231-5400
    C: (512) 658-1554
     
     
     
     
     
  • 0 in reply to Alan Neidig
    TI__Guru**** 244440 points
    Hello Alan

    Again blank. I would suggest copying the image into a doc file and then attaching (don't drag and drop the file) using the "Use rich formatting" link on the bottom right of the replay pane.

    Regards
    Amit
  • 0 in reply to Alan Neidig
    TI__Guru**** 244440 points
    Hello Alan

    Looking at the image QUES 1: Is the FSS image with a Pull Up Connected?

    Also at any point during the image the FSS does not go down to 0V. And the manner in which it goes down suggests that the driver side IO has some issue. On the TM4C SSI Slave, the IO is an input unless the IO settings got changed to an Output!!!

    Regards
    Amit
  • 0
    Intellectual 255 points
    Will take a look.
     
    Have you had a chance to review the initial register settings.  Any concerns?
     
    Alan
     
  • 0
    Intellectual 255 points
    Feedback to your questions …
     

    1.     No external pull up or pull down.  When an external pull down is added and the SSI module is initialized, the FSS does go all the way to 0v.  If the external pull down is removed and internal an internal pull down is enabled (either on the Tiva or the Nordic), the line looks like the scope shot I sent.  The line never gets to 0v.  We also tried increasing the drive strength on the Nordic from standard (0.5ma) to high (5.0ma).  All of these combinations had the same result - the line didn't go to 0v.

    2.     There should be no way the Tiva line is configured as an output GPIO_PCTL shows that PF0-PF3 are all configured for alternate function 0x0E (14d).


    Alan

     
  • 0 in reply to Alan Neidig
    TI__Guru**** 244440 points
    Hello Alan

    PF0 is a locked pin, so I am expecting that the unlock was done (though that is not the issue here either as FSS is on PF2). Configuring the PCTL and AFSEL will allow the peripheral to control it. Just having PCTL is not sufficient.

    I would like to see the configuration of the GPIO's in this case.

    Also if possible, can you isolate the two devices and probe the FSS from the Nordic device?

    Regards
    Amit
  • 0
    Intellectual 255 points
    Amit,
     
    Response from customer … Are you available for a conference call with customer Monday?
     
    The PCTL and AFSEL registers are shown in the previous screenshots. We haven't had much varying effect from unlocking the PF0 pin. Which, by the way, do we ever re-lock that pin?
     
    All config / relevant code is in the attached c file.
     

    For item #3, we have already done it.   We took the exact code and put it on a Nordic development board.  It worked perfectly.

    Your thoughts,
    Alan
     
     
     
  • 0 in reply to Alan Neidig
    TI__Guru**** 244440 points
    Hello Alan

    I checked the C file and the first thing that struck me was SysCtlClockSet. This API is not valid for TM4C129x and must be removed. Similarly if there is any call to SysCtlClockGet API, then it must be removed as well.

    The SSI Slave Register configuration looks fine and wanted to confirm if the SSICLK between the master and slave is supposed to be 1MHz.

    Did they check the IO after isolating the two sides?

    Regards
    Amit