I am using QSSI port 2, single data line transmission. While developing a driver for it discovered some unexpected behavior and wanted to know if there is any explanation for what I see, or if it should be added to the errata.
My setup:
Single bit (not dual or quad), configured as master, Gpio control of chipselect, Rx/Tx FIFOS, interrupt driven, using system clock as input to module.
What works:
My custom board communicates just fine with the device. I get the data I expect.
Interrupts fire and I get into the ISR to transfer data from the RxFifo, re-fill the TxFifo.
RxFifo half full or more interrupt and TxFifo half empty or less are observable in the raw interrupt status.
What I didn't expect:
Using the CCS debugger to display SSI Regs caused RxFIFO data to be removed one at a time for each single step I performed.
The Rx timeout and Tx End of Transmission never showed up for me in the raw interrupt status register as I would have expected. Rx Fifo Not Empty bit was 1, and it didn't matter how much time I waited - the Rx Timeout bit in the raw interrupt status never appeared. Tx Fifo WAS empty, but I never got an end of transmission interrupt either.
As a work-around, I wrote a function in my driver to determine if the transaction was complete. I had to resort to checking if I had less than 4 bytes (FIFO is 8 bytes) remaining to complete the transfer, and if so, I manually pull data from the RxFifo if it was not empty.
The most important information I wish to understand is this: Under what circumstances/configuration might the Rx Timeout and Tx End of Transmission bits in the raw interrupt status register be inhibited? I am NOT looking at the masked interrupt status.
Thanks.
