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DMA Concurrency



The technical reference (p679) states:

20.2 Module Operation The DMA acts as an independent master in the platform architecture. DMA will attempt to execute up to two channels at the same time to maximize system throughput. 

My concern was that this may imply that high priority DMA channels (SPI, SCI, etc) could starve lower priority DMA channels.  When I tested it out, the lower priority DMA channels received the data just fine, even when the higher priority channels were not being triggered.  I believe I may be mis-understanding how the Technical Reference is describing concurrent transfers and DMA channel arbitration.

In all, can I assume that all revisions of the RM57 will ensure that higher priority channels will not starve lower priority channels?  If not can you provide some additional guidance on what factors may invalidate this assumption.

  • Hello Stephen,

    The priority scheme is something that must be considered carefully. Just as with the interrupt priority, it is possible to overwhelm the system throughput and spend all of your time servicing requests for a particular entity. With that said, I think it is highly unlikely that a particular channel is completely overlooked/ignored. My concern would be if it could be serviced in sufficient time that keeps the data from being overrun in the data source.

    Unfortunately, I am not aware of any methodology or tools to use to analyze this type of bandwidth concern. The only methodology that might be possible is to look at the frequency of the higher priority data transfers vs. time it takes to transfer to see if there are any times where the other data might get through.