The technical reference (p679) states:
20.2 Module Operation The DMA acts as an independent master in the platform architecture. DMA will attempt to execute up to two channels at the same time to maximize system throughput.
My concern was that this may imply that high priority DMA channels (SPI, SCI, etc) could starve lower priority DMA channels. When I tested it out, the lower priority DMA channels received the data just fine, even when the higher priority channels were not being triggered. I believe I may be mis-understanding how the Technical Reference is describing concurrent transfers and DMA channel arbitration.
In all, can I assume that all revisions of the RM57 will ensure that higher priority channels will not starve lower priority channels? If not can you provide some additional guidance on what factors may invalidate this assumption.