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Use Core SysTick of Cortex instead of RTI on TMS470MF06607

Riccardo Capponi
Prodigy 60 points

I needed to use all of RTI TMS470, so I started to read the ARM documentation and tried to use the SysTick, that in the datasheet of the micro I have not found and in fact there is (in Cortex Core) another undocumented timer from TI. Below you find the code of the core peripheral:

typedef volatile struct SysTick
{
        uint32_t STCTRL;
        uint32_t STRELOAD;
        uint32_t STCURR;
        uint32_t STCALIB;
} SysTick_t;
#define SysTickREG ((SysTick_t *) 0xE000E010)

Link to the documentation:

infocenter.arm.com/.../index.jsp

I don't know if there are particular reasons for don't use it.

Kind Regards

Riccardo capponi

  • TI__Genius 11645 points
    Riccardo,
    One of our TMS470M expert will help you on this.
  • TI__Guru 59540 points
    Hello Riccardo,

    This feature is documented within the ARM Cortex-M3 TRM available through the ARM website. The specific version of the core used in this device is r2p0 so it is recommended to reference the specific TRM for that core version. systick specific information can be found in section 8.2 NVIC Register Descriptions. Specifically they can be found starting at figure 8-3 through 8-5 or tables 8-4 through 8-6.

    In regard to usability of this specific feature, I am not aware of any reason it cannot be used. However, there is mention of a reference clock to drive the counter that is not implemented so the only mechanism is to drive the counter with GCLK (core clock) which is the same as HCLK in the case of this device.

    Another point to note is in regard to NVIC. The interrupt controller for this device is primarily the M3VIM which is a proprietary interrupt controller used for increased compatibility with legacy devices/architecture. The M3VIM manages interrupts mapped to NVIC channels 0x10-0x8F as well as M3VIM channels 0-47. System exceptions remained mapped to the NVIC channels 0x0 - 0xF due to the tight coupling with the M3 core. For additional information NVIC vector table configuration please see table 8-1 of the device TRM (spnu495c) as well as programmer's model information in section 8.3 of the same document.
  • in reply to Chuck Davenport
    TI__Guru 59540 points

    Hello Riccardo,

    For some reason, the suggest/verify answer buttons are not showing on this thread so I can't tell if this information was helpful to you. Please let me know if the information has helped to resolve your problem so I may close the thread.