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TMS570 SCI: combined idle-line/multi-buffered/RX DMA Mode

Rainald Koch
Intellectual 610 points


I have searched the Reference Manual, SPNU515B, Sect. 29.2.4.1, 29.2.5, 29.4.1, and 29.5.1 for the SCI RX behavior in combined idle-line/multi-buffered/RX DMA mode. Three questions remain:

Is the ISR for the address-frame interrupt responsible to transfer that frame or is it to be included in the DMA transfer(s)?

Does the HW reset the buffer address on a valid idle period, so that each [address byte | first data byte] ends up in [edited, the LSB of] RD0, even if a previous telegram had less bytes than expected (with or without detection of a bit-frame error)?

I guess that the interrupt generated on address frames is a receive interrupt but it could also be a wakeup interrupt, since TXWAKE is involved in sending idle periods.

  • 0
    TI__Guru**** 191886 points

    Hi Rainald,

      I came across this unanswered post. Let me see if I can answer your questions.

      Whether to generate interrupt or DMA request on the address frame is configurable. If you go to table 30-2 in the TRM you will generate interrupt or DMA request on a reception of a address frame depending on the settings of the SET_RX_INT, SET_RX_DMA and SET_RX_DMA_ALL bits.

      For your second question, are you in reference to use the DMA or not? The DMA has no idea about an idle period. If the previous telegram has lesser bytes than expected then the DMA does not know and will transfer the remaining bytes that belongs to the next telegram.

      The wakeup interrupt is an interrupt if the SCI recevies a data while it is in low power mode state.

     

     

  • 0 in reply to Charles Tsai
    Intellectual 610 points

    Hi Charles,

    thank you for the hint to Table 30-2 in Section 30.4.1. That section is answering both the first and third question (RX INT must not be set for IRQs to be generated for address frames only). It would be nice to have Section 29.4 reduced to a reference to 30.4 instead of incomplete information.

    The 2nd question is not about DMA but the buffer of the SCI module.

    regards,
    Rainald