We have developed a TM4C based device, now in production. Unfortunately we have discovered problems with the latest software release. For a particular unit (i.e. most units does not display this problem), about one in five start ups fails. Investigations show that the device hangs in the fault ISR due to a bus fault occurring when writing to the VREF bit of the ADCCTL register.
The ADC peripheral is enabled just before the VREF bit is accessed, i.e. the recommended delay of 3 system clocks between clock enable and register access mistakenly has been omitted. This piece of code is however old and we cannot understand why the problem has arisen now between two software revisions. By inserting a single NOP randomly the problem can go away (e.g. 20 lines of code before enabling the peripheral or 15 lines after does the trick, but not 20 lines after - same function, no optimization). Stack size has been increased without improvements. It seems like code size/placement affects the behavior and vulnerability for lacking delay after peripheral enable, but how?
I just want to understand the circumstances as it feels like there is something to learn from this.
Best Regards,
Johan