Hi,
tldr: is there a way to emulate the TI SSI interface using mibspi?
I have an application where I'm trying to get a continuous bit stream transmitted and received through mibspi. Previously, I used a standard SPI interface in the TI synchronous serial interface (SSI) format. A detailed description of such an interface is described on page 749 of the datasheet here:
http://www.ti.com/lit/ds/symlink/lm3s9b92.pdf
I'm going to describe the rest of my problem using a transmitter as an example.
In my previous application (see pg 749 on linked data sheet), there was a TX FIFO that could be filled up. Data is streamed out the FIFO, and when the FIFO is half empty (or other programmed level), an interrupt is generated, and the CPU can refill the FIFO as part of an interrupt handler. This results in a continuous output stream since the FIFO always has data contents in it. A deep FIFO gives you more time for other tasks since interrupts would be generated less frequently.
From what I understand, using the mibspi in either compatibility or multibuffer mode does not have a feature to generate interrupts for a "half-empty" buffer.
In compatibility mode, tx data is loaded into the TXBUF register and then moved into the TX shift register. A interrupt can generated when TXBUF is empty, but that is basically a 1-deep FIFO. Interrupts would need to be serviced for every single 16-bit transfer.
In multibuffer mode, tx data is loaded into RAM. An interrupt is not generated until the entire RAM contents have been transmitted. Then you could reload the RAM with new data to transmit. In both these cases, there could be gaps in the transmit stream if you cannot service the interrupt fast enough or gaps simply due to C2TDELAY, T2CDELAY etc.
Basically, is there a way to emulate the TI SSI interface using mibspi?
Thanks for any help!
