RM57 Memory Initilization

Other Parts Discussed in Thread: HALCOGEN

In the Datasheet:

http://www.ti.com/lit/ug/spnu562/spnu562.pdf

There seems to be a contradiction, in section 2.5.1.21 MINITGENA is defined to have 0xA in bits [3-0] to enable hardware initialization however in section 2.5.1.22 it is defined that for auto initialization to be enabled MINITGENA must be 0x5h. 

Could this be clarified?

Also the memInit code generated by halcogen is listed as:

_memInit_
        ldr   r12, MINITGCR     ;Load MINITGCR register address
        mov   r4, #0xA
        str   r4, [r12]         ;Enable global memory hardware initialization
        ldr   r11,  MSIENA      ;Load MSIENA register address
        mov   r4, #0x1          ;Bit position 0 of MSIENA corresponds to SRAM
        str   r4, [r11]         ;Enable auto hardware initalisation for SRAM
mloop                           ;Loop till memory hardware initialization comletes
        ldr   r5, MSTCGSTAT
        ldr   r4, [r5]
        tst   r4, #0x100
        beq   mloop
        mov   r4, #5
        str   r4, [r12]         ;Disable global memory hardware initialization
        bx lr
        .endasmfunc

Looking at section 2.2.4.2 it is stated that MSINENA must be set, but it is not in the generated code. Does this mean L2 SRAM region 0x08000000 0x0800FFFF is initialized? or that nothing is initialized? 

Thanks!

Dmitri