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Two additional clocks in EPI GP mode

Micha Nisani
Intellectual 390 points
Other Parts Discussed in Thread: TM4C129DNCPDT

Hi

I get 2 CPU clock after each read with the following configuration (16 bit data , 12 bit address):

Usally read is two CPU clock , but after the read I have two additional cpu clocks to next operation read or write.

My configuration:

 /////// EPI_FPGA_CONFIG = (EPI_GPMODE_CLKPIN | EPI_GPMODE_ASIZE_12 | EPI_GPMODE_DSIZE_16)

 EPIDividerSet(EPI0_BASE, 4);

 EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL);

EPIConfigGPModeSet(EPI0_BASE, EPI_FPGA_CONFIG, 0, 0); 

EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_64KB | EPI_ADDR_RAM_BASE_6);

When I read 16 or 32 bit from the EPI , I get after each read, two additional CPU clock.

for write I get burst of write.

Is it Bug in the Chip ?

thx

  • 0
    TI__Guru**** 244400 points
    Hello Micha,

    Since you have opened 2 posts, I would respond to this one. Do note that the EPI Divider is set for divide by 4. Hence while in the earlier post the user was getting 1 additional clock, they were using a divider of 2. In this case due to the divider being used at 4 the number of clocks will increase between the two access.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Intellectual 390 points

    Hi Amit

    My cpu clock is 120Mhz. The Epi need to run at 20Mhz. So I use Epi divider 4. I get two extra 20Mhz clocks after each read, not 120Mhz clocks.

    The divider is use to set the epi clock, so I do not understand. The extera w clocks.

  • 0 in reply to Micha Nisani
    TI__Guru**** 244400 points
    Hello Micha,

    OK. Let me check the configuration and its impact on the clocking. One information that I need is how is the application is setup to access the external device. Is it using HWREG macro for the address space 0x6000.0000 ?

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Intellectual 390 points

    Here is example to my access code to HW

    #define FPGA_BASE_ADD 0x60000000

    #define ADD_B0 (FPGA_BASE_ADD + (0x000<<1)) // shift left , we use 12 bit address , A0 is actually A1.
    #define ADD_B1 (FPGA_BASE_ADD + (0x100<<1))
    #define ADD_B2 (FPGA_BASE_ADD + (0x200<<1))

     uint32_t     *Address;

    uint16_t  data;

    uint32_t  data_32;

     Address = ADD_B1;

     *((uint16_t *)Address) = data; // write 16 bit data 

     data = *((uint16_t *)Address); // read 16 bit data 

    data_32 = *Address; // read 32 bit data (two 16 bit read)

    // I do not write 32 bit data.

    // After each Read 16 or 32 bit , I get two more EPI clocks (20Mhz)

    thx

  • 0 in reply to Micha Nisani
    TI__Guru**** 244400 points
    Hello Micha

    I ran the code and what I see is that the 16 bit write and read have a common frame select high @ 20MHz with Write high for one clock and read high for one clock. Then the 32 bit read comes with frame and read high for one 20MHz clock, followed by a idle cycle and then again frame and read high for one 20MHz clock. At no point I see 2 additional EPI clocks.

    So I made a small change of adding a write after the 32 bit read and I saw 2 additional EPI clocks. This is because the internal EPI state machine works of the divided clock and requires state transition time.

    Regards
    Amit