I have an application where I have a TM4C1294ncpdt connected to an FPGA via it's EPI. I am trying to figure out the best mode to configure the host-side interface in so that I can write the fabric side. Ideally, the FPGA appears as a memory mapped extension of the CPU and accesses will stall the CPU as the read and write delays could be variable. I don't need high performance as most transactions will be single reads and writes. The interconnect I would ultimately like to have is a connection to a Wishbone or AXI bus in the fabric side hence the need to handle variable delay. Any suggestions are welcome.
Thanks,
Jon
