Hi ,
I am transitioning a design from Stellaris LMS9B90 to TM4C1294KCPDT .
In Stellaris PA0-PA5 was assigned for SSI0 and PA6 was used for CCP1 . Is it possible to use this pin combination in Tiva for SSI0(PA0-PA5) and T3CCP0(PA6) ?
I used Tiva Pin Mux utility to check the pin configuration and it shows the above combination works.
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_SSI0);
//
// Configure GPIOA_3 as the SSI Chip Select
//
ROM_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3);
ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);
//
// Configure GPIO Pins for SSI0 mode.
//
ROM_GPIOPinConfigure(GPIO_PA2_SSI0CLK);
ROM_GPIOPinConfigure(GPIO_PA4_SSI0XDAT0);
ROM_GPIOPinConfigure(GPIO_PA5_SSI0XDAT1);
ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_2);
SSIConfigSetExpClk(SSI0_BASE, g_ui32SysClock, SSI_FRF_MOTO_MODE_3,
SSI_MODE_MASTER, 1000000, 8);
SSIEnable(SSI0_BASE);
Referring to the code above - Does SSIEnable() function enable PA0-PA7 as SSI or just enables the configured pins PA0-PA5 ?
What should I do differently to make sure that Port A is configured only in Legacy Mode. If configured correctly what will be the value of GPIOA_DIR register ?
Thanks,
Chandana