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CCM error forcing mode failed

Fatemeh Ehsani-besheli
Intellectual 510 points

Other Parts Discussed in Thread: TMS570LS20216, HALCOGEN

Hi,

I have been trying to perform the CCM self-test on TMS570LS20216. The step in our implementation of the error forcing mode is the same as sys_selftest.c of the HalcogenTMS570LS31x generated file.

CCMKEYR = ERROR_FORCING_MODE;

/* Wait till error-forcing is completed. */

while (CCMKEYR != 0U)

{

}/* Wait */

 

/* check if compare error flag is set */

if ((esmREG->ESTATUS1[esmGROUP2] & 0x4U) != 0x4U)

{

/* ESM flag is not set */

CCM_SELF_CHECK_FAIL3

else

{

/* Check FIQIVEC to ESM High Interrupt flag is set */

if((vimREG->FIQINDEX & 0x000000FFU) != 1U)

{

/* ESM High Interrupt flag is not set in VIM*/

CCM_SELF_CHECK_FAIL4

}

As it's mentioned in the reference manual, the ESM error flag is expected after completing the error forcing mode. In our code, the interrupt occurs and the esmGroup2Notification function is executed but I receive the CCM_SELF_CHECK_FAIL3 fail notification which means the ESM group2, channel2 status register has not been set. By removing the while loop which waits for the completion of error forcing mode, the CCM_SELF_CHECK_FAIL3 message does not appear but the next fail notification (CCM_SELF_CHECK_FAIL4) occurs. 

Can you help me to find out what is wrong with this code?

Sincerely,

Fatemeh

 

  • 0
    TI__Guru 69070 points

    Fatemeh,

    Do you have in the ESM interrupt routine this type of code?:

    void esmHighInterrupt(void)
    {
        /* Note : Group 1 Error           */
        /*   1 to  32 -> channel 0  to 31 */
        /*  65 to  96 -> channel 32 to 63 */
        /* 129 to 160 -> channel 64 to 95 */
        /* Note : Group 2 Error           */
        /*  33 to  64 -> channel 0  to 31 */

        uint32 vec = esmREG->IOFFHR - 1U;

    /* USER CODE BEGIN (50) */
    /* USER CODE END */

        if (vec < 32U)
        {
            esmREG->SR1[0U] = (uint32)1U << vec;
            esmGroup1Notification(esmREG,(vec));
        }
        else if (vec < 64U)

    The line that writes back the vec value "esmREG->SR1[0U] = (uint32)1U << vec;"

    will clear the ESM status register that you are testing in the main line code.

    So if you have this, then the flag you are looking at is probably being set but then cleared by the ISR

    before you ever get to test it in your "C" program.

  • 0 in reply to Anthony F. Seely
    Intellectual 510 points
    Anthony,

    As you mentioned, the status register is cleared by the ISR before being checked in my code.
    I had commented the line that clears the status register for group2 channel2 (ESTATUS1[esmGROUP2] & 0x4U) in the ISR, the next time, i have set it by zero to leave the bits unchanged, but the problem exists and I get the fail message.
    if (vec >= 32U)
    {
    //esmREG->ESTATUS1[1U] = 1U << (vec-32U);
    esmGroup2Notification(vec-32U);
    }
    On the other hand, in this type of processor, there is only “ESM channel 0-31” tab in the ESM field, and the channel 31 is also disabled. Overall I want to know, is it possible to test the CCM?
    Is it sufficient that the interrupt routine occurs and the program goes to the notification function?
    I mean I need to be sure that the error forcing mode works correctly, so if anytime an error occurs in the core compare module, the program goes to my safety defined function, for example being reset.

    Regards,
    Fatemeh
  • 0 in reply to Fatemeh Ehsani-besheli
    Intellectual 510 points
    My question about disabling the “ESM Channel 31 in Halcogen” has been resolved. I understand that I can enable it just by putting esmEnableInterrupt(0x80000000U) command after esmInit() function, but my other questions still remain.
  • 0 in reply to Fatemeh Ehsani-besheli
    TI__Guru 69070 points
    Fatemeh,

    Hi my mistake. The read of IOFFHR before the switch/case statement:

    uint32 vec = esmREG->IOFFHR - 1U;

    also clears the ESMSR bit.

    From TRM SPNU503B page 407:
    "Note: Reading the interrupt vector will clear the corresponding flag in the ESMSR2 register; will not clear ESMSR1 and ESMSSR2 and the offset register gets updated."

    Please put a breakpoint on this line and check that the bit is set before the vector is read, then at least we know for sure the issue is that the ISR clears the status bit.

    The answer may be to read the shadow status bit for (ESMSSR2)register, which keeps a history until cleared by software.
  • 0 in reply to Anthony F. Seely
    Intellectual 510 points
    Anthony,

    Thanks for your replay, I understand that the ESMSR1 and ESMSR2 are both cleared by the interrupt service routine.
    As you've mentioned the read of offset register (IOFFHR) clears the ESMSR2 and has not any effect on ESMSR1 But this statement “esmREG->ESTATUS1[0U] = 1U << vec” clears the ESMSR1. So both register are cleared by the ISR.
    Your answer about reading the ESM shadow register is applicable in “error forcing mode” but it seems that in “self-test error forcing mode” the shadow register is not set.
    My answer is if we enable the interrupt; we can check the shadow register or ESM key register to see if any error occurred and by disabling the interrupt we can check the ESM status register.
    In the Halcogen example, the interrupt is not enabled and my mistake is to put “_enable_FIQ()” in the code that cause clearing the flags.

    Thanks and Regards,
    Fatemeh