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TM4C1294 SPI slave: transmit problem


I am developing a custom board, based on a TM4C129 MCU, which integrates several components that use SPI protocol. In all components except one, this MCU is master and everything goes fine. But when slave, I do not manage to make it work.
The component to which the MCU is connected is an AD converter that must be powered up by following a recommended sequence (take reset line low for a period of time and write the two control registers).
In most discussions I have found in this forum dealing with the MCU as a slave, the MCU just reads, and does not write except for one (e2e.ti.com/.../453608).

I think that the problem I have is more due to understanding of the SPI protocol principle than a problem of coding (maybe or probably there is also a coding problem). When I write to the 32-bit control register of the ADC by calling ROM_SSIDataPut four times (4 bytes), the last byte is transmitted continuously, i.e. it is not just send once, but non stop. Why does it happen? what could be pushing the MCU to send  the byte continuously?

As the MCU is acting as a slave, the CLK and nFSS are controlled by the ADC (master). The nFss is always logic low after reset.

Below is the SSI setting:

//
// The SSI0 peripheral must be enabled for use.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);

//
// For this example SSI0 is used with PortA[5:2].  GPIO port A needs to be
// enabled so these pins can be used.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

//
// Configure the pin muxing for SSI0 functions on port A2, A3, A4, and A5.
// This step is not necessary if your part does not support pin muxing.
//
GPIOPinConfigure(GPIO_PA2_SSI0CLK);
GPIOPinConfigure(GPIO_PA3_SSI0FSS);
GPIOPinConfigure(GPIO_PA4_SSI0XDAT0);
GPIOPinConfigure(GPIO_PA5_SSI0XDAT1);

//
// Configure the GPIO settings for the SSI pins.  This function also gives
// control of these pins to the SSI hardware.  Consult the data sheet to
// see which functions are allocated per pin.
// The pins are assigned as follows:
//      PA5 - SSI0Tx
//      PA4 - SSI0Rx
//      PA3 - SSI0Fss
//      PA2 - SSI0CLK
//
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 |
               GPIO_PIN_2);

//
// Configure and enable the SSI0 port for SPI master mode.
//
SSIConfigSetExpClk(SSI0_BASE, g_ui32SysClock, SSI_FRF_MOTO_MODE_0,
                   SSI_MODE_SLAVE, 5000000, 8);

// Enable the SSI0 module.
//
ROM_SSIEnable(SSI0_BASE);

Another question, after writing the four bytes, I add
ROM_SSIDataPutNonBlocking (SSI0_BASE, ui8AddrByte1); /* Argument[31..24] */
ROM_SSIDataPutNonBlocking(SSI0_BASE, ui8AddrByte2); /* Argument[23..16] */
ROM_SSIDataPutNonBlocking(SSI0_BASE, ui8AddrByte3);  /* Argument[15..8] */
ROM_SSIDataPutNonBlocking(SSI0_BASE, ui8AddrByte4 ); /* Argument[7..0] */

//
// Wait until SSI0 is done transferring all the data in the transmit FIFO.
//
//while(ROM_SSIBusy(SSI0_BASE));

Another question, after writing the four bytes, I add ROM_SSIBusy as shown below

ROM_SSIDataPutNonBlocking (SSI0_BASE, ui8AddrByte1); /* Argument[31..24] */
ROM_SSIDataPutNonBlocking(SSI0_BASE, ui8AddrByte2); /* Argument[23..16] */
ROM_SSIDataPutNonBlocking(SSI0_BASE, ui8AddrByte3);  /* Argument[15..8] */
ROM_SSIDataPutNonBlocking(SSI0_BASE, ui8AddrByte4 ); /* Argument[7..0] */

//
// Wait until SSI0 is done transferring all the data in the transmit FIFO.
//
while(ROM_SSIBusy(SSI0_BASE));

and the code gets stuck. Is it that normal?

Thanks,
Gello

  • Hello Gello,

    Better to use the blocking SSIDataPut function instead of the non blocking version. The blocking function writes data only after the FIFO is empty. Once this works you can switch to the non blocking version.

    Thanks,
    Sai
  • Sai,

    Thank you for your answer.
    I try both blocking and non blocking versions, but the result was the same: the byte is continuously sent by the MCU.

  • does the txfifo will send the 8th last  item when master tries to read data? TM4c123 spi does so.

    i am not sure 1294 does so too or not?

    in my case, i will fill up the txfifo 8 more items all zerod. then validate the data is zero or not.

  • Gello said:
    the last byte is transmitted continuously, i.e. it is not just send once, but non stop. Why does it happen?  What could be pushing the MCU to send  the byte continuously?   

    My friend - have you not clearly stated that the TM4C MCU acts as "Slave" in your usage - described here?   Thus - is not the "Continued clocking by the ADC" (the Master in your case) a (very) high suspect in your issue?    Don't you agree that any "slave SPI device" will only send data in response to the "master SPI device's" clocking?

    Further - you note that, "nFss is always logic low after reset."   If that's (really) the case - how ever is "any" Slave device to be released from the transaction?

    I believe that your ADC's "continuation of clocking" AND its "never toggling" of nFss deserves (some) attention...   Neither matter is addressed in your writing...

  • Hi cb1-,
    Indeed ADC's "continuation of clocking" is the first suspect of all this mess. You are certainly right.
    Can I conclude from this analysis that a device acting as a slave transmits something (last byte stored in the fifo) each time the clock bus is "clocking"?

  • Hi Gello,

    Thank you - yet I don't know that we can draw that conclusion. Usually - the Master "ends" the SPI transaction by releasing nFss. More SPI clocks may then arrive (@ your device) but these usually prove "harmless" and are "unnoted" by the "released" Slave.

    I suggest that you thoroughly review your Master ADC's SPI timing chart - looking specifically for its mechanism to "de-assert" nFss. (the ADC vendor will likely employ a different term/designation.)

    I've an idea as to how you can "force" this "nFss release" - but best to hold that in reserve until (and if) you complete your ADC data review...
  • Thank you, CB1, for your answer.
    The device is an AD7763. There are two "nFss": one (nFSI) handled by the slave (by me) to announce a writing to the registers, and another (nFSO) handled by the ADC that is active low during a reading. From the ADC point of view, the first is an input line, and the second is a output line. There is another active-low output line (nDRDY) to announce a new conversion is ready. After analyzing the ADC's timing chart, I understood that the nFss of SPI protocol should be nFSO as the ADC is the master.

    Below is how I connect the different lines:
    MCU <--> ADC
    SSI0CLK<--> SCO
    SSI0TX <--> SDI
    SSI0RX <--> SDO
    SSI0FSS <--> nFSO

    For me, it has no sense that after a reset procedure, both nFSO and nDRDY are logic low. The only reason I found is that after a RESET, the ADC is powered off and these lines are left low to enable the power-on procedure consisting in writing a sequence to the ADC's control registers.

    After having read many posts, I know that you do not like debugging other vendor's problem (if this is one of them), but have you ever faced a similar scenario?

    I thank you for the time you spend to read and answer to my posts.
  • You provide such detail - and such care in writing - it is hard to deny you. But please - firm/I are embedded @ a giant - I "come up for air" briefly - look for interesting posts here (such as yours) & "fast/furiously" respond - as best I can.

    I can tell you that I find it "rare" that an ADC can "play Master."   As you note - a sequence is required to properly power & format the ADC's control registers - this seems to indicate that your ADC (really) is NOT a Master!    Does you data sheet make that (ADC is the master) statement - if so please do identify page & para.
     
    If you can wait till tonight - and link to that device's data sheet - I'll read & see what can (or might) be done...

  • Thanks again for the time you spend.

    Here is the link to the data sheet:

    www.analog.com/.../AD7763.pdf

    In the data sheet it is not explicitly said that the ADC must play master, so when I started trying to make it work for a few days, I considered the ADC as slave. The problem was that there was a collision in the clock bus, as SCO (Serial Clock Output)  is an output line and SSI0CLK is also output. Moreover, nFSO is also an output pin.  (see timing charts in page 6, pin description in page 8 and 9, and power-up sequence in page 21)

    Then, after having read posts from a lot of forums, I found somewhere that the ADC had to play master. I do not have the link right here because I am not writing from my computer, but it must be saved there. Anyway, as I said, SCO and nFSO are generated by the ADC, so it seems logical that the MCU be slave.

    Tomorrow I will take much attention to what it is said about the Serial Data Input used in the power-up sequence procedure: "The first data bit (MSB) must be valid on the next SCO falling edge when SCP = 0 after the nFSI event has been latched"

  • Like cb1 I found the idea of ADC playing master unusual so I took a quick look at the data sheet. A few thoughts until someone takes a closer look.

    My first thought was that someone appears to have gone out of their way to make the interface complex. I'm sure there's a reason but I'd need time to figure out why it might be organized in this fashion. It does have to be master on conversion but apparently not on setup. It appears to have an IIC interface, perchance that can be used for configuration?

    I would not put another device on the spi with this one, at least initially. That's asking for trouble. It does document that the chip select only goes low for 32 clock cycles, also that the master conversion clock must be running for the spi to work. It might be useful to put a tristate buffer on the data out so you can disconnect it when it's not wanted, likewise the chip select. That might make debugging smoother.

    You definitely need to get 'scope or logic analyzer captures of the clock, master clock and chip select to see if the i/ o is performing as expected.

    Robert
  • I've just carved out the time to read/review your device's data-sheet - and WOW!   You did not alert nor warn that yours is, "24-bit, 625 kSPS, 109 dB Sigma-Delta ADC w/ On-/Chip Buffers - & multiple serial interfaces.   (SPI & I2S)   Where to begin?

    • should you not have a "Pro board" you have "NO Chance" (not even a small one) of harnessing the power of such a device
    • As poster/friend Robert notes - the SPI interface has a (bit) of a split/dual (bi-polar) personality.  And is beyond complex!   (may require as many "mental health" visits as do I)    Chip seeks your MCU to behave (first) as SPI Master (I believe) to program the internal Registers - but then "shape shifts" and orders your MCU into SPI Slave to receive.   I'm not sure that we can abide by all of the timing requirements - and even achieve this.   Surely will not be simple - nor straight-forward.
    • You must supply "MCLK" master clock input - and this "impacts" the "SCO" (output) clock from this ADC - but not in any "normal/customary" manner that I can discern - even after 30 minutes of battle w/the 32 pg. datasheet.   And - worse still - can this "SCO" signal "relate properly" to the MCU's normal SPI_CLK signal expectations?   Really?  
    • Pg 21 "Using the AD7763" supplies the necessary "Start-Up" procedure.   While ADI's datasheet claims "SPI" - and I've used SPI w/success for years - figure 3, "Register Write" does not reveal just how you'd clock in SPI Data - as you earlier noted - only "SCO" which is an output from the ADC is shown.   The "normal" SPI_CLK does NOT appear (anywhere!) w/in key/critical "SPI Timing Diagrams" (both read & write) w/in Pg. 6!   ADI's calling this an SPI interface appears more fanciful/wishful - that reality!

    It is likely that Robert & I - together - could "piece this interface out" should few more hours land (along w/"Brink's truck") in each day.   But in reality - there is NO guarantee - and I cannot speak for "Robert's free time."

    Clearly you've many questions to ask - and "ADI" (your device's maker) is the (clear) place to start.   Ask them just how one would normally "marry" MCLK w/the normal/customary SPI signals (you've well listed those) to achieve Fig. 3 - and then Fig. 2.   (I'd not be surprised if their response took (some) time.)

    At minimum - that vendor should provide a diagram detailing "just how" the "normal/customary" SPI signals are to be "teased/massaged" into compliance w/the very NON-STANDARD (surely NON-SPI Interface) revealed across Pg. 6.  (alleged SPI Timing diagram)

    Must you (really) use this chip?   I hate to leave you - again you MUST have a pro-board - chip is costly - chip maker must arrive & guide you in answer of "HOW" you are to manage Figure 3 & Figure 2, "SPI Timing" Pg. 6, datasheet.   It is "beyond" non-standard - I've not seen anything (ever) quite like this...

    I fear Robert's/my cry of, "Uncle" is very much required (and echoes) - in this case...   Chip maker is your best (likely only) resource at this stage...   Should you have a "deadline" - extend it - immediately!   Really I'd look for a chip which follows (some) recognized signal protocol - yours does NOT!

  • Agree wholeheartedly here, and a key question has to be why this chip?

    Robert
  • Than you cb1 and Robert for your clarifying explanations.

    The more I work on this ADC, the more I realize that it will be difficult to make it compatible with the TM4C1294. Yesterday, I managed to power it up and then to power it down with the MCU acting as a master, but at a low frequency clock (5 MHz). If I increase it up to 10 MHz, it does not work. I will try to make the power-up sequence work with the MCU as slave, but even if it worked, the big issue will be reading from the ADC. The problem lies on the time synchronization that the ADC requires and marrying the two clocks. As you say (cb1), the question is: can this "SCO" signal "relate properly" to the MCU's normal SPI_CLK signal expectations? So, as you two suggest, I will first work with the eval board and then, you will go back to my custom board.

    As far as the choice is concerned, I was advised to use this ADC which proposes great features in terms of sample rate, quantization and programmable filters. But if you know other ADCs with similar features, I will take them seriously into account and modify the board design.

    Again, thank you for the time you two spend to understand my problem.

  • Thank you too, Gello - for your well constructed and thoughtful posts. Never would Robert nor I have (even) considered responding to post's (cleverly & precisely) reporting,  "MCU Does not work!"   (did someone near, just yell, "retarded?")

    You are "silent" in reporting your effort in contacting your ADC chip vendor!    That's not good!
    My firm works w/them - we provide tech support (along w/eval board design) over a band of "new products" not including your current device.

    As past written - your concerns - echoed here by both Robert & myself - are (surely) best handled by the chip maker. You should ask them, "Just how one is to manage the (supremely) complex, "receipt of data via "SCO" which may clock (outside) of the expectations of normal/customary SPI design?"   That is - and remains - their job to resolve to your satisfaction.

  • I did write both to their forum and to the technical support: for the Engineer Zone, no answer since a week and I wrote them before doing it here, and for the technical support, they told me they were not able to support me personally in a timely manner and proposed to contact the engineer zone.
    Nonetheless, I am sure that they will give a solution, but I will have to wait a little bit more. Anyway, I will let you know if I find a solution in case another reader may run into the same problem.

  • Thanks for that clarity - while posters Robert & cb1 have (some) skills/experience - that ADC's interface is "so" non-standard that hours would be required to understand it - and even then - success may not be guaranteed.

    The "success" of common interfaces such as "SPI" is their known, "marching to a prescribed beat." Neither the "band nor conductor" of your ADC appears in lockstep w/normal/customary SPI. That's the (real) issue - as best you, Robert & I see things.

    I've been at this forum (and several others) forever - have never encountered that IC. (perhaps now - we three - know the reason...)

    My firm does much design/development work on/around analog measurement - yet 24 bits most always proves, "a beast" and usually we're able to meet client goals w/16-20 bit ADC resolutions - even far less when/where "highest speed acquisition" is demanded.   Sometimes - but not always - you may be able to satisfy your analog requirement by using two (or more) ADCs - each one fulfilling key (yet different) aspects of your design need...

  • Agreed with cb1 that the vendor is the best source for determining how to interface, check for application notes and eval boards. Even if they use a different processor any application note may prove useful. I have dismissed some sigma-delta convertors from consideration for use because their interface required either an FPGA or a specific processor.

    Having said that, I believe this

    Gello said:
    I was advised to use this ADC which proposes great features in terms of sample rate, quantization and programmable filters

    gets to the heart of the matter.

    The question you should be asking (or providing known answers to) are

    • What is the necessary sample rate (or frequency response)?
    • What is the signal level and range?
    • What is the desired accuracy?
    • What other characteristics are important (precision, noise rejection, etc...)?

    Then you can look for solutions (of which the converter is a part).

    Robert

    BTW if you expecting anywhere close to 24bit accuracy, I'd advise you to stop now and seriously re-evaluate your goals.

  • @Robert,

    Has your (sync'ed to cb1's Cesium) clock - once again - drifted?   (you'll note my 09:39 response - on the money!)    24 bits - indeed...

  • I suspect the synchronization cable's tension is being modified in anticipation of east coast precipitation warnings.

    Unless you have paid attention to accuracy before you are likely surprised by how difficult it is to actually perform accurate measurements when every suppliers headline for converters is 24 bits resolution. And if you then start pricing accurate references you may need to keep someone with first aid experience handy.

    Robert
  • Robert Adsett said:
    in anticipation of east coast precipitation warnings.

    Might that be your (always) understated manner in describing, "30 inches of SNOW?"   And - if that sync cable (has) sagged - must be - "your end!"

    Requirements for 24 bit ADC success:  (per famed poster Robert)

    • deep pockets ($$$)
    • licensed M.D. on premises
    • exhaustive tissue supply (to damp the tears)

    So Robert - (now) we know why you've rejected my kind/inspired offer of 3V6 zener (device made on/around 1972 - same date as one here, btw) as "not fully suitable" as pristine voltage reference.   (Picky you, Robert)

    Let the record show that not all posters must comply w/poster Robert's "tres exactement" standards...  (not to note - sagging sync cable)

  • Well a paramedic is probably sufficient.

    Also I'm concerned that customs would block import of such a device as that zener, clearly the layer of dust on it could carry agricultural parasites.

    Off-topic in another direction, is it per-chance glass encased?

    Robert
  • Robert Adsett said:
    Off-topic in another direction, is it per-chance glass encased?

    Off topic?   Off topic - is this not, "Open Lines, Friday?"

    Indeed pristine device IS glass encased!   And the protective "coating" you note has served admirably as, ESD "deflector."   (we're told that ESD cannot harm that which it cannot see!)  

    500 on the way (w RCMP sticker - per your request) - customs be damned!

  • OLF it is.

    I was thinking of the problems these glass encased devices had with sensitivity to light. There are tales told of circuit issues that were cured with electricians tape over glass encased diodes (they turned into photo-detectors under light). I also recall a tale of one manufacturers subsequent epoxy shell being insufficiently opaque to IR and exhibiting some of the same symptoms.

    I'm sure the constabulary will give the shipment all the due consideration it deserves.

    Robert
  • Robert Adsett said:
    ...cured with electricians tape over glass encased diodes (they turned into photo-detectors under light)

    WHAT/WAIT - issue cured?   Are you implying that our (regular) practice of applying fine black tape - may be no longer required?

    Please alert (constabulary) 500 diodes (glass encased) along w/100 rolls (fine black tape) arriving via "Alberta Express" your dock - Monday morn.   (due consideration - indeed...)