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TMS570 DCAN Module Extended and Standard

Other Parts Discussed in Thread: HALCOGEN

We have an application in which we use 6 message boxes, we use this configuration: 

1: Send Extended identifiers
2: Send Standard identifiers
3: Receive standard message with identifier 665
4: Receive Extended messages (all identifiers)
5: Receive Standard messages (all identifiers)
6: Send standard message with identifier 666

We send and receive on interrupt basis. send, hten on interrupt all other messages in the buffer are send

receiving on interrupt puts teh message in a buffer

The problem is: We don't receive any Standard identifier messages. There is no interrupt generated on the moment i send the message.

The code is all generated by halcogen and then changed to have the desired functionality

So my question is: 

1: Is it possible to send extended AND standard messages on 1 CAN channel

2: Why are we not receiving the standard messages?

  • Update on original question: With the given configurations we DO receive extended, AND also standard messages with ID 665, so we receive interrupts on messagebox 3 and 4. When change message box 4 and 5, so new configuration is:

    3: receive standard with ID 665
    4: receive standard (all)
    5: receive extended (all)

    With this new configuration we still receive messages on box 3, so standard with ID 665, we also receive standard messages but,
    now we DO NOT receive extended anymore.
    So we receive messages that generate an interrupt on box 3 ad 4 again.

    So what could be the problem?
  • As you have already realized, HalCoGen has a single check box to determine standard or extended ID's. That checkbox determines how the ID and Mask fields are interpreted. Do you mind sending me your modified HL_can.c file? I have never mixed standard and extended IDs in the same CAN module, but it should be supported. I will ask around.
  • this is the file. Its just some changes from the generated file. The Mailbox configuration is changed to:

    /** - Initialize message 1
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU));
    canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)1U & (uint32)0x1FFFFFFFU) << (uint32)0U);
    canREG1->IF1MCTL = 0x00001080U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF1CMD = (uint8) 0xF8U;
    canREG1->IF1NO = 1U;

    /** - Initialize message 2
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U);
    canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)2U & (uint32)0x000007FFU) << (uint32)18U);
    canREG1->IF2MCTL = 0x00001080U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF2CMD = (uint8) 0xF8U;
    canREG1->IF2NO = 2U;

    /** - Initialize message 3
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U);
    canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x665U & (uint32)0x000007FFU) << (uint32)18U);
    canREG1->IF1MCTL = 0x00001080U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF1CMD = (uint8) 0xF8U;
    canREG1->IF1NO = 3U;

    /** - Initialize message 4
    * - Wait until IF1 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF1 control byte
    * - Set IF1 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00000000U & (uint32)0x1FFFFFFFU));
    canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0U & (uint32)0x1FFFFFFFU));
    canREG1->IF2MCTL = 0x00001080U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF2CMD = (uint8) 0xF8U;
    canREG1->IF2NO = 4U;

    /** - Initialize message 5
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x00000000U & (uint32)0x000007FFU) << (uint32)18U);
    canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0U & (uint32)0x000007FFU) << (uint32)18U);
    canREG1->IF1MCTL = 0x00001080U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF1CMD = (uint8) 0xF8U;
    canREG1->IF1NO = 5U;

    /** - Initialize message 6
    * - Wait until IF2 is ready for use
    * - Set message mask
    * - Set message control word
    * - Set message arbitration
    * - Set IF2 control byte
    * - Set IF2 message number
    */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U);
    canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x666U & (uint32)0x000007FFU) << (uint32)18U);
    canREG1->IF2MCTL = 0x00001080U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
    canREG1->IF2CMD = (uint8) 0xF8U;
    canREG1->IF2NO = 6U;

    We got a temporary solution by receiving all messages in box 4 and then check ourself if its standard or extended.
  • That is a good solution. The feedback I got from our CAN experts thinks that with mail box 4 being all messages with standard ID, that when an extended ID message comes in, the CAN state-machine sees that the ID matches the filter so it stops comparing to other mailboxes even though the message is not captured because it is an extended ID.