TMDX570LS31HDK - ESM Group 3, Channel 7, unrecoverable error in Flash wrapper (FMC)

Martin,
Have you programmed the Flash ECC?

Best Regards,
Kevin Lavery

Hello,

Thanks for the fast answer.

I have used default settings. I did not turn on/off something on purpose -
Maybe by accident during investigation - I do not know.
How can I double check if I have programmed Flash ECC ?

New Input:
It seems power cycle HDK Board (disconnect USB and external Power supply) changes
the behavior. In other words before power cycle the check fails (Esm_Stat3 != 0) and after
power cycle the check is ok ((Esm_Stat3 == 0).

BR
Martin

Martin,
I do not know what state the device is in at the end of programming.
If the code always works after it has been power-cycled, do you still have a problem?

Best Regards,
Kevin Lavery

After end of programming Code Composer switch to Debug Perspective.

It seems the code below is executed and then the CPU hangs in for (;;). 

Resume and Go is deactivated (grey). The user can press Terminate to exit Debug mode.

Power cycle changes something. I did not expected changes of flash with/without

powercycle. I do not remember , but I  think somewhere that errors can be read

and/or cleared. Maybe this happens with power cycle ?

If I do not power cycle and just press Terminate and Debug (Program again) then the 

error exists. 

After  power cycle I loose the current debug session. Therefore it is not a workaround. 

void _c_int00(void)
{

/* USER CODE BEGIN (5) */
/* USER CODE END */

/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();

/* USER CODE BEGIN (6) */
/* USER CODE END */

/* Initialize Stack Pointers */
_coreInitStackPointer_();

/* USER CODE BEGIN (7) */
/* USER CODE END */

/* Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
*
* Errata Description:
* The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on
* Workaround:
* Clear ESM Group2 Channel 2 error in ESMSR2 and Compare error in CCMSR register */
if (DEVICE_ID_REV == 0x802AAD05U)
{
_esmCcmErrorsClear_();
}

/* USER CODE BEGIN (8) */
/* USER CODE END */

/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();

/* USER CODE BEGIN (11) */
/* USER CODE END */

/* Workaround for Errata CORTEXR4 66 */
_errata_CORTEXR4_66_();

/* Workaround for Errata CORTEXR4 57 */
_errata_CORTEXR4_57_();

/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset.
*/

/* check for power-on reset condition */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
{
/* USER CODE BEGIN (12) */
/* USER CODE END */

/* clear all reset status flags */
SYS_EXCEPTION = 0xFFFFU;

/* USER CODE BEGIN (13) */
/* USER CODE END */
/* USER CODE BEGIN (14) */
/* USER CODE END */
/* USER CODE BEGIN (15) */
/* USER CODE END */
/* continue with normal start-up sequence */
}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
{
/* Reset caused due to oscillator failure.
Add user code here to handle oscillator failure */

/* USER CODE BEGIN (16) */
/* USER CODE END */
}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
{
/* Reset caused due
* 1) windowed watchdog violation - Add user code here to handle watchdog violation.
* 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
*/
/* Check the WatchDog Status register */
if(WATCHDOG_STATUS != 0U)
{
/* Add user code here to handle watchdog violation. */
/* USER CODE BEGIN (17) */
/* USER CODE END */

/* Clear the Watchdog reset flag in Exception Status register */
SYS_EXCEPTION = WATCHDOG_RESET;

/* USER CODE BEGIN (18) */
/* USER CODE END */
}
else
{
/* Clear the ICEPICK reset flag in Exception Status register */
SYS_EXCEPTION = ICEPICK_RESET;
/* USER CODE BEGIN (19) */
/* USER CODE END */
}
}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
{
/* Reset caused due to CPU reset.
CPU reset can be caused by CPU self-test completion, or
by toggling the "CPU RESET" bit of the CPU Reset Control Register. */

/* USER CODE BEGIN (20) */
/* USER CODE END */

/* clear all reset status flags */
SYS_EXCEPTION = CPU_RESET;

/* USER CODE BEGIN (21) */
/* USER CODE END */

}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & SW_RESET) != 0U)
{
/* Reset caused due to software reset.
Add user code to handle software reset. */

/* USER CODE BEGIN (22) */
/* USER CODE END */
}
else
{
/* Reset caused by nRST being driven low externally.
Add user code to handle external reset. */

/* USER CODE BEGIN (23) */
/* USER CODE END */
}

/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case.
* An ESM group3 error only drives the nERROR pin low. An external circuit
* that monitors the nERROR pin must take the appropriate action to ensure that
* the system is placed in a safe state, as determined by the application.
*/
if ((esmREG->SR1[2]) != 0U)
{
/* USER CODE BEGIN (24) */
/* USER CODE END */
/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
for(;;)
{
}/* Wait */

Martin,
When you have finished programming, could you execute a system reset? (Run->Reset->System Reset)
Do you still see problems?
Kevin

I cannot press reset (see screenshot below). 

I found a Workaround: 

I disable all Self tests in

HAL Code Generator - 

Tab TMDX570LS3137HDK

Tab SAFETY INIT

It seems then nothing is checked and the HDK board starts and executes application. 

Turn off hardware checks is not a general solution/workaround but acceptable for my current project.

Martin,
As you said, disabling checks is not advised in general.
In your screenshot, it looks like you may not be connected.
Best Regards,
Kevin Lavery