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SPI TI frame format: inversion

Gello
Intellectual 390 points


Hi,

I'm using a TM4C1294NCPT mcu. The data sheet states that in the Texas Instrument Synchronous serial frame format, the SSInFss is always low and is pulsed high for one SSInCLK period when transmitting data.

I would like to know if there is any register bit that inverts this behavior, that is, the SSInFss is always high and is pulsed low for one SSInCLK period.

Some modes of the Freescale format drive SSInFss low for half a period when transmitting, not for a full period as I would like. 

Thank you

  • 0
    Guru 47900 points

    Pardon - but if the signal proves correct - but inverted - does not a simple (external) hardware inverter, (properly) "Blip your radar?"  (does to mine)

  • 0 in reply to cb1
    Intellectual 390 points
    Yes, indeed, but if the MCU can do it, I do not need to add an inverter to the board.
  • 0 in reply to Gello
    Guru 47900 points
    My friend - that's often (always) the case - and days, weeks, months are "LOST" trying to, "tease out" that which is, "At your doorstep."

    If you're building 100K units - such saving may make sense.

    In addition - I guarantee that you'll (always) find some use for the extra output capability & buffering potential of so valuable a component...
  • 0 in reply to Gello
    Guru 27665 points
    To re-quote the old Maxim "Premature optimization is the root of all evil"

    I agree with cb1, you've got to be building a lot of boards to spend very much time worrying about the cost of an inverter. An hour's worth of design effort buys a lot of inverters.

    Robert
  • 0 in reply to Robert Adsett
    Guru 47900 points

    Let the record show that (both) posters Robert et cb1 have a (slight) surplus of inverters. (not that that impacts our advice - much!)
    If you're brave enough to purchase from a "back-room" - behind another "back-room" - quite a "deal" may be nego'ed...

  • 0 in reply to cb1
    Intellectual 390 points

    Thanks for your answers.

    So I solve it with a logic gate.

  • 0 in reply to Gello
    Intellectual 620 points

    If your timing allows for it, you can always configure your FSS line as GPIO rather than SSI. You can then use the write API to set the CS to any logic level that works for slave device. No inverter IC needed in this case.

  • 0 in reply to VG
    Guru 47900 points

    Yes - that has worked - but "breaks" from the MCU's dedicated, SPI sub-system.  

    Most any "real-world" design will require - and benefit - from (some) signal inverters.   Saving a sub 0.50 (USD) component cost - while "breaking" from the tried/true API - registers as "second best" impo...

  • 0 in reply to cb1
    Intellectual 620 points
    I am not against using inverters. But there are tradeoffs between the two different approaches. (ie - maybe board space or component count are an issue)

    I just thought I would present another option for the OP and leave it up to them to weigh the tradeoffs and decide what works best.
  • 0 in reply to Gello
    TI__Guru 59540 points
    Hello Gello,

    The economics/practicality regarding adding an external inverter not withstanding, TM4C does not have the capability to invert this signal internally so the only way to achieve this is to add the inverter externally.
  • 0 in reply to Chuck Davenport
    Intellectual 620 points
    Chuck,

    Is it possible to configure the CS as GPIO and invert it that way?
  • 0 in reply to VG
    Intellectual 390 points
    Thanks Vincent.
    That was my first idea, which I have already used in other applications. The problem lies on the fact that I need to synchronize FSS and data lines so that a clock period after driving FSS low I have to clock in data. For instance, for 5-MHz clock, a delay of 200 ns between the two events. If my tests were right, I did not get such delay with SysCtlDelay. I think the shorter delay was 1,4 µs.
  • 0 in reply to Gello
    Intellectual 620 points
    Gallo,

    I think I understand your problem better and agree that using GPIO to control CS for this problem would not work.
  • 0 in reply to Gello
    Guru 47900 points

    Some here - far earlier & presenting more detail than vendor's rep - are (rightly) slighted by the award of, Verified Answer to one (vendor's late arriving rep) who simply repeated what had (long) past been stated!

    If you seek to (encourage) a week's delay in responding - your award system surely pushes in that direction!

  • 0 in reply to cb1
    Intellectual 390 points
    Sorry cb1, please don't take it in the wrong way. My initial question was whether it was possible to invert the behavior of the TI frame format. You gave me a solution that I implemented with a NOT gate, but not the answer to my question. I clicked "Verify answer" to Chuck's one because he clearly said "no, the TM4C does not have this capability".