Hello
It seems EMIF changes the sequence of write/read statements.
We have :
* Code Composer Studio Version: 6.1.2.00014
* TMDX570LS31HDK (= TMS570LS3137)
* HAL Code Generator 04.05.01
We connected FPGA via EMIF (Asynchronous Device) :
EMIF Setting in HAL Code Generator :
Read Setup = 1 Cycle
Read Strobe = 8 Cycle
Read Hold = 1 Cycle
Write Setup = 1 Cycle
Write Strobe = 8 Cycle
Write Hold = 1 Cycle
TA = 0 Cycles
EMIF Clock 12.5 MHZ
Extend Wait Enabled
MAX_Extended_Wait = 255
Select Strobe Mode enabled
Write From CPU to external device: 0x0D0E0C0F (OK; as expected; On EMIF Bus Write 0x0D0E and Write 0x0C0F)
Write From CPU to external device: 0x01020304 (OK; as expected; On EMIF Bus Write 0x0102 and Write 0x0304)
Breakpoint (Sleep - do something else in app)
Read From external device from a location (OK, as expected; on EMIF bus we see the read)
Breakpoint (Sleep - do something else in app)
Read From external device from same location (NOK, on EMIF bus nothing happens, but in application a value is returned)
Breakpoint (Sleep - do something else in app)
Write From CPU to external device: 0x05060708 (NOK; On EMIF Bus Write 0x0506 and Write 0x0708 and Write 0x0000 to the addres + 1)
I think that the CPU caches the data that I read or write to the device. (Because the second read is not visible on EMIF)
According to the documentation of the MPU, it should be possible to enable
or disable caching in in the MPU.
In HAL Code Generator I can configure for each region base address, size, end address, type,
and permission. But there is no flag to configure whether it is cacheable.
I have configured type as DEVICE_NONSHAREABLE for my region (Based Addres 0x60000000).
Similar Effect if Type STRONGLYORDER_SHAREABLE is configured.
How we can force the correct sequence of write statements ?
How we can force read from hardware for every read request ?
How we can enable/disable cache within HAL-Code Generator ?
How we can double check setting in Application Code?
Best regards,
Martin
