TMS570 Uart Bootloader SCI

Hi,
Are you in SCI mode or LIN mode? Can you make sure the SCIGCR1.6 bit is 0 so the LIN/SCI module is operating in SCI mode?

I also want to know if you can toggle the TX pin in GIO mode. If you do the below, do you see the TX pin goes high?

gioSetDirection(sciPORT2, 0x4); // set TX pin to output pin
gioSetBit(sciPORT2, 0x4, 0x1); // set TX pin to high

Make sure that you are in digital I/O mode for the above test with SCIPIO0=0x0. You can do the above test in the debugger too.

Hi.

Thanks to all for your replies,

I have attached  document and source code of bootloader. i have tms570ls31. Charles you are right, Bootloader code using SCI-LIN port, and i want to change to SCI port. i looked at pinmux.

void Gladiator_PINMUX_SCI2()
{
*(int *) 0xFFFFEB30 = 0x01010102;//P8 //SCITX
*(int *) 0xFFFFEB2C = 0x01020101;//P7 //SCIRX
}

I could not see problem on pinmux. 

void Gladiator_PINMUX_NHET2()
{
*(int *) 0xFFFFEB14 = 0x01010401;//p1 //NHET2[18]
*(int *) 0xFFFFEB18 = 0x01020108;//p2 //NHET2[2],NHET2[0]
*(int *) 0xFFFFEB1C = 0x01020101;//p3 //NHET2[4]
*(int *) 0xFFFFEB20 = 0x10100102;//p4 //NHET2[10],NHET2[8],NHET2[6]
*(int *) 0xFFFFEB24 = 0x01040101;//p5 //NHET2[12]
*(int *) 0xFFFFEB28 = 0x01020108;//p6 //NHET2[16],NHET2[3]
*(int *) 0xFFFFEB38 = 0x01040101;//p10 //NHET2[7]
*(int *) 0xFFFFEB3C = 0x01010104;//p11 //NHET2[9]
*(int *) 0xFFFFEB48 = 0x02010101;//p14 //NHET2[5]
*(int *) 0xFFFFEB64 = 0x01010102;//p21 //NHET2[3]
*(int *) 0xFFFFEB68 = 0x01040402;//p22 //NHET2[11],NHET2[13],NHET2[1]
*(int *) 0xFFFFEB6C = 0x01010104;//p23 //NHET2[15]
}

SCI init is

void sciInit(void)
{
/** @b intalise @b SCI1 */
unsigned f;
double vclk = SYS_CLK_FREQ * 1000000 / 2;

/** - bring SCI out of reset */
sciREG1->GCR0 = 1U;

/** - Disable all interrupts */
sciREG1->CLRINT = 0xFFFFFFFF;
sciREG1->CLRINTLVL = 0xFFFFFFFF;

/** - global control 1 */
sciREG1->GCR1 = (1 << 25) /* enable transmit */
| (1 << 24) /* enable receive */
| (1 << 5) /* internal clock (device has no clock pin) */
| (0 << 4) /* number of stop bits */
| (0 << 3) /* even parity, otherwise odd */
| (0 << 2) /* enable parity */
| (1 << 1) /* asynchronous timing mode */
| (0 << 0);

/** - set baudrate */
// sciREG1->BAUD = 42; /* 115.20K baudrate for 160MHz Vclk */
// sciREG1->BAUD = 259; /* 19.2K baudrate for 160MHz Vclk */
// sciREG1->BAUD = 155; /* 19.2K baudrate for 96MHz Vclk */

f = sciREG1->GCR1 & 2 ? 16 : 1;
sciREG1->BAUD = ((unsigned)((vclk /(f*UART_BAUDRATE) + 0.5)) - 1) & 0x00FFFFFF;

/** - tranmision length */
sciREG1->LENGTH = 7; /* length is 7+1 */

/** - set SCI pins functional mode */
sciREG1->FUN = (1 << 2) /* tx pin */
| (1 << 1) /* rx pin */
| (0); /* clk pin */

/** - set SCI pins default output value */
sciREG1->DOUT = (0 << 2) /* tx pin */
| (0 << 1) /* rx pin */
| (0); /* clk pin */

/** - set SCI pins output direction */
sciREG1->DIR = (0 << 2) /* tx pin */
| (0 << 1) /* rx pin */
| (0); /* clk pin */

/** - set SCI pins open drain enable */
sciREG1->ODR = (0 << 2) /* tx pin */
| (0 << 1) /* rx pin */
| (0); /* clk pin */

/** - set SCI pins pullup/pulldown enable */
sciREG1->PD = (1 << 2) /* tx pin */
| (1 << 1) /* rx pin */
| (0); /* clk pin */

/** - set SCI pins pullup/pulldown select */
sciREG1->PSL = (1 << 2) /* tx pin */
| (1 << 1) /* rx pin */
| (1); /* clk pin */

/** - set interrupt level */
sciREG1->SETINTLVL = (0 << 26) /* Framing error */
| (0 << 25) /* Overrun error */
| (0 << 24) /* Pariry error */
| (0 << 9) /* Receive */
| (0 << 8) /* Transmit */
| (0 << 1) /* Wakeup */
| (0); /* Break detect */

/** - set interrupt enable */
sciREG1->SETINT = (0 << 26) /* Framing error */
| (0 << 25) /* Overrun error */
| (0 << 24) /* Pariry error */
| (0 << 9) /* Receive */
| (0 << 1) /* Wakeup */
| (0); /* Break detect */

/** - inialise global transfer variables */
g_sciTransfer[0].mode = 0 << 8;
g_sciTransfer[0].length = 0;

/** - Finaly start SCI1 */
sciREG1->GCR1 |= 0x80;

i could not see problem on sci init. function. When i change memory map of the SCI and SCI-LIN resgisters, code should work and i should communicate with SCI port. But i Should not communicate.

i thought it would be a problem with baud rate.  VCLK1 is 80 mhz, its source is pll1 and both of them was  the required value . I do not understand problem.

0550.spna193.zip1425.spna193.pdf