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Internal EEPROM wear leveling -- TM4C12X

Marshall Folkman
Intellectual 720 points

I am working with the TM4C123 Launchpad. I need to calculate the endurance of my system. Particularly, I need to be able to calculate how long my application's EEPROM is rated for. I know that the TM4C12X MCU's have "Built-in wear leveling", but the TM4C12X datasheet(s) do not specify the type of wear leveling implemented (static/global or dynamic). The datasheet's only explanation is that it has an...

"Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion)

to 15M operations (when cycling through two pages ) per each 2-page block." - top of page 53

I don't understand what this means. For example, if there is 2kB of EEPROM and I have exactly 2kB of memory that I want to store and update once every second, how many seconds is my program rated for? 500K seconds? Less? More? How does the MCU Define a "Page"? 

How do you calculate exactly what a program is rated for?

Thank you.

Marshall

  • 0
    Guru 27665 points

    The parameter you are looking for is EPECYC. Number of program/erase cycles of a single word before failure, specified at 500,000. Note this is 5x the flash equivalent so wear leveling is taken into account.

    So ~138 Hrs at 1Hz

    Robert

  • 0 in reply to Robert Adsett
    Guru 27665 points
    Also do take a look at the EE errata, they are rather severe.

    Robert
  • 0 in reply to Robert Adsett
    Intellectual 720 points
    Robert,

    Thank you for your quick reply. Your answer makes sense, but just to clarify one point. Is it true that the less memory I choose to "take up" in the above example will give me more available writes? For example, if I choose to write only 0.5kB to 2kB of EEPROM, does this mean that I can now rate the endurance to 4 x (138 Hours) = 552 hours?

    In other words, does the wear leveling technique distribute wear to all memory cells equally? (Also known as global wear leveling)
    I know that some wear leveling techniques (dynamic wear leveling) do not necessarily do this. They instead just chop up the memory into pages that may be larger than the amount of data being used so that the leftover memory on each page never gets used.

    I just want to be sure that the wear leveling technique used distributes wear to ALL memory available.

    Marshall
  • 0 in reply to Marshall Folkman
    Guru 27665 points
    There's no indication that it does distribute the wear levelling unless you do so manually and I'd not be inclined to think it did.

    If you really need something like 1Hz writing there is no EE technology available that I'm aware of that makes sense (the TI EE emulation even less so, take a look at the maximum write times as well as the errata). If you are doing enough writes to ask this question I'd switch to a different memory technology.

    Robert