RM48L952ZWT SPI Interface: /CS and CLK

Hello.  I am trying to glean some information in regards to the RM48L952ZWT SPI interface chip select and clock lines.  My question(s) is for a given SPI interface (i.e. MibSPI5 or other) you may have multiple chip select lines, thus you can chose any one to function as your /CS.  Can you also use all 4 to function as individual chip selects to interface to multiple devices that will communicate on the SPI5 bus only?  Hence, the firmware would control which SPI5 /CS is active.  The second question is how are the SPI clocks generated and controlled, where do they come from in the processor?  Thank you.