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[TM4C1294NCPDT] - EPI in HB16 and Quad-chip Select.

Evripidis Karseras
Intellectual 735 points

Other Parts Discussed in Thread: TM4C1294NCPDT

Hi all,

I have a rather question with a feeling that the answer to it is quite simple but I am unable to find. Here it goes.

Is it possible to setup the EPI to HB16 (XFIFO mode) and have 4 external devices, i.e., CS0n, CS1n, CS2n and CS3n ?

I stumbled upon something that might suggest a contradiction; I am referring to "tm4c1294ncpdt.pdf" and more specifically to:

1) Table 11-9  (p. 833-835) where only CS0n and CS1n are mentioned

2) Table 11-7 (p. 829-830), in the last 4 lines where it is suggested that HB16 in XFIFO mode (0x3) is possible to have 4 external devices.


Can you please clarify the above or point me towards the right direction please ?


Regards,

Evros

  • 0
    TI__Guru 59540 points
    Hello Evros,

    In the datasheet/userguide you mentioned, the following paragraph from p.928 may be helpful:

    "If one of the Quad-Chip-Select modes is selected (CSCFGEXT is 0x1 and CSCFG is 0x2 or 0x3 in
    the EPIHBnCFG2 register), both the peripheral and the memory space must be enabled. In the
    EPIADDRMAP register, the EPADR field is 0x3, the ERADR field is 0x3, and the ECADR field is 0x0.
    In this case, CS0n maps to 0x6000.0000; CS1n maps to 0x8000.0000; CS2n maps to 0xA000.0000;
    and CS3n maps to 0xC000.0000. The MODE field of the EPIHBnCFGn registers configures the
    interface for the individual chip selects, which support ADMUX or ADNOMUX. If the CSBAUD bit is
    clear, all chip selects use the mode configured in the MODE bit field of the EPIHBnCFG register.
    Table 11-5 on page 864 gives a detailed explanation of chip select address range mappings based
    on which combinations of peripheral and memory space are enabled."

    I believe that this clearly indicates that quad-cs is supported.
  • 0 in reply to Chuck Davenport
    Intellectual 735 points

    Hello Chuck,


    Thank you for your answer.

    I did read the paragraph that you suggest more times than I care to admit. But on what pins of the EPI0 ? The relevant table showing the pin connection sonly mentions two CS pins when XFIFO is selected on the HB16.

    I was going to try tomorrow to write a simple loop and test each pin separately. I mean, I could not find anything else in the datasheet. I might have missed something though.

    Regards,

    Evros

  • 0 in reply to Evripidis Karseras
    TI__Guru 59540 points

    Hi Evros,

    Look in table 11-4 CS modes 0x5 and 0x6. Quad-CS mode pin assignment is given in this table.

    "EPI0S30 is used as CS0n and EPI0S27 is used as CS1n. EPI0S34 is used as CS2n and EPI0S33 is used as CS3n."

  • 0 in reply to Chuck Davenport
    TI__Guru 59540 points
    Sorry. Table 11-4 not 11-6. Made the correction to the prior post.
  • 0 in reply to Chuck Davenport
    Intellectual 735 points
    Chuck,

    It is you are correct. I agree. Thank you for repeating this.

    Please see Table 11-7, 833-836, and see that the aforementioned pins, also in your reply are not to be found anywhere. The way the text is structured does not reflect this, which I do not doubt, I trust that you know what you are talking about, I have used the forum before and you guys know your stuff. The way it is put out is that those pins are indeex CS0n-CS3n, if other modes (ADMUX/ADNOMUX) but not XFIFO.

    Is this an erratum ? Please let me know if I am being wrong somewhere. I am quite new at this line of products fo T.I but not in readin datasheet.

    Kind Regards,
    Evros
  • 0 in reply to Evripidis Karseras
    Intellectual 735 points
    Hi Chuck,

    @Post Feb 4, 2016 11:11 PM

    Does not change anything. Same information in 11-4 and 11-6 regarding Quad CS pins.

    Evros
  • 0 in reply to Evripidis Karseras
    Intellectual 735 points
    Excuse me; Table 11-9. I believe it's time I called it a day !!!
  • 0 in reply to Evripidis Karseras
    Intellectual 735 points
    I meant it is already late over here in the U.K. I was not being disrespectful. I apologise if you thought that was the case Chuck.

    Regards,
    Evros
  • 0
    TI__Guru**** 244440 points
    Hello Evros

    XFIFO can work only with 2 chip selects. The more pressing issue is that the FIFO Full and Empty flags are single, hence additional logic would be required for FIFO Full and FIFO empty from 2 XFIFO's to be put together.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Intellectual 735 points

    Hi Amit,


    What you say makes more sense. Thanks.

    As a side note; are the FIFO empty and FIFO full input signals also able to be disabled ? I believe they are right ? Not that it would make any difference to the availability of an extra two CS signals.

    What is the suggested way of interfacing 4 identical devices, e.g., ADCs to the EPI (assume 3-state data lines) ? Controlling the CS signals manualy I suppose, correct ?  If address mode is used then obviously we are wasting a couple of cycles when writing the address but we gain 4 CS signals and nice integration to the EPI framework.


    Let me know what you think.


    Regards,

    Evros

  • 0 in reply to Evripidis Karseras
    TI__Guru**** 244440 points
    Hello Evros

    What device are you interfacing over EPI? It would be helpful to understand the target device to be able to analyze.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Intellectual 735 points
    Hi Amit,

    It is only 4 ADCs which I want to stream data out of so very simple as you can tell. The interface is parallel with a tri-state data bus and a BUSY signal output. A CSn as well obviously.

    I am new with the Tiva API and MCUs so until I can get the gist of them I am asking all these question. In the end I could just use GPIO pins and DMA, but if the EPI can do it for me and by using the driver library then even better. I could get the basic functionality and then try and optimise if need be.

    Regards,
    Evros
  • 0 in reply to Evripidis Karseras
    TI__Guru**** 244440 points
    Hello Evros,

    Again, details makes the difference. How wide is the ADC, whether data is streamed at both edges or a single edge (which one if single)? What is the polarity of the BUSY signal?

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Intellectual 735 points
    Hello Amit,

    I will get back to this as I am in the middle of something else atm.

    Regards,
    Evros
  • 0 in reply to Evripidis Karseras
    TI__Guru**** 244440 points
    Hello Evros

    Sure.

    Regards
    Amit