TMS570LC4357 EMIF clock jitter

Hi Tom,

No we don't provide any data on EMIF_CLK output jitter.

From the PLL and from the oscillator - you should expect a very small (<<1ns) contribution because that PLL also needs to feed the CPU clocking at 300MHz and if there were even 1ns jitter in the PLL that would be almost 30% of the clock frequency. If you budget 500ps this is probably conservative.

It's more likely that you'll have trouble at the board level to be honest, with errors in the edge due to signal integrity problems.
Definitely make sure to terminate the EMIF_CLK as it's the most critical of the EMIF signals.