Hello all,
I ran into the same issue about SSI+DMA completion interrupt as in this thread posted by Christian Voglhober, https://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/361916.
Is anyone here successful to find a solution for the issue?
My app should transfer/receive continuously some data via SSI-slave using TM4C1292NCPDT. So my approach is using SSI and DMA with ping-pong transfer mode.
It worked fine with Stellaris but when it comes to porting it toTiva-C I encountered the issue.
When a transfer with the PRI channel finishes, in the ISR DMATXRIS bit in SSIRIS register cannot be cleared by writing '1' to DMATXIC in SSIICR as datasheet says.
It looks cleared after both disabling TXDMAE in SSIDMACTL and writing '1' to DMATXIC.
However, DMATXRIS is set again by re-enabling TXDMAE even if the ALT channel transfer is still in progress (not completed).
This ends up with re-entering the ISR forever and nothing can be executed any more.
Additionally, as described in the datasheet to clear DMATXRIS, disabling TXDMAE bit is a helpless method because my app should keep transferring in ping-pong mode.
I think that this issue is going to an errata and wondering why it is not explained in an errata after the first post by Christian in Aug 2014.
Amit, a TI employee, mentioned it was planned to an errata in the thread.
Anyway, I need a workaround for it. Please give me any suggestion and advise.
