A question about EPI uDMA interrupts

Jeff McDevitt

Other Parts Discussed in Thread: TM4C129XNCZAD

Hello,

I am using the TM4C129XNCZAD on a custom board with the EPI connected to an FPGA. I am able to read/write to the FPGA using the EPI direct calls fine.

Now I am trying to use the uDMA to read from the FPGA. I am trying to read one burst of 8 to get started. Everything seems to work but after the data is read the EPI Interrupt fires continuously. It appears to be because the DMARDRIS bit in the EPIRIS register (indicating the uDMA read is complete) is set. The data sheet states that this bit is cleared by writing to the DMARDIC bit in the EPIEISC register. If I do this using the CCS Debugger, then the bit is cleared and the EPI interrupt no longer fires. If I try to due this in the interrupt handler using a HWREG call it doesn't clear. I am wondering if there is a better way to do this (using a DriverLib call for example) or if I am missing the EPI/uDMA concept completely.

Thanks,

Jeff

over 9 years ago

0 Amit Ashara over 9 years ago

TI__Guru**** 244400 points

Hello Jeff

A code which shows how it is being done by the program will be more useful for any debug

Regards
Amit

0 Jeff McDevitt over 9 years ago in reply to Amit Ashara

Expert 1775 points

I have attached the test program.

Fullscreen 5353.main.c Download

/*
 * main.c
 */

#include <stdint.h>
#include <stdbool.h>
#include <string.h>

#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_gpio.h"
//#include "inc/hw_ints.h"
#include "inc/tm4c129xnczad.h"

#include "driverlib/epi.h"
#include "driverlib/pin_map.h"
#include "driverlib/gpio.h"
#include "driverlib/sysctl.h"
#include "driverlib/interrupt.h"
#include "driverlib/rom.h"
#include "driverlib/udma.h"
#include "driverlib/systick.h"


#include "utils/ustdlib.h"

uint32_t g_ui32EPIStatus;
uint32_t g_ui32RxCount;
uint32_t g_ui32DMAErrCount;
uint32_t g_ui32EPIErrors;
uint32_t g_pui8Buffer[1024];
uint32_t g_ui32SysTickCount;
uint32_t g_EPIIntCount;
uint32_t g_TargetBufferIndex;

// The control table used by the uDMA controller.  This table must be aligned to a 1024 byte boundary.
#pragma DATA_ALIGN(dmaControlTable, 1024)
tDMAControlTable  dmaControlTable[1024];


#define FAULT_SYSTICK           15          // System Tick

//----------------------------------------------------------------------------//
//---                        SysTickIntHandler                             ---//
//----------------------------------------------------------------------------//
void SysTickIntHandler(void)
{
  g_ui32SysTickCount++;
}

void PinoutSet(void)
{
    // Enable all the GPIO peripherals.
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOR);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOS);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOT);

}

//----------------------------------------------------------------------------//
//---                           DMAIntHandler                              ---//
//----------------------------------------------------------------------------//
//--- This interrupt handler is only used for software-only DMA transfers. ---//
//--- Clearing the interrupt is not required. See spmu363A p551            ---//
//----------------------------------------------------------------------------//
void DMAIntHandler(void)
{

}



void DMAErrHandler(void)
{
    uint32_t ui32Status;

    ui32Status = uDMAErrorStatusGet();

    if(ui32Status)
    {
        uDMAErrorStatusClear();
        g_ui32DMAErrCount++;
    }

}

void initEpi(void)
{
	// The EPI0 peripheral must be enabled for use.
	SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);

	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
	SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);

	// Enable pin PK5 for EPI0 EPI0S31
	GPIOPinConfigure(GPIO_PK5_EPI0S31);
	GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_5);

	// Enable pin PN3 for EPI0 EPI0S30
	GPIOPinConfigure(GPIO_PN3_EPI0S30);
	GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_3);

	// Enable pin PN2 for EPI0 EPI0S29
	GPIOPinConfigure(GPIO_PN2_EPI0S29);
	GPIOPinTypeEPI(GPIO_PORTN_BASE, GPIO_PIN_2);

	// Enable pin PB3 for EPI0 EPI0S28
	GPIOPinConfigure(GPIO_PB3_EPI0S28);
	GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_3);

	// Enable pin PB2 for EPI0 EPI0S27
	GPIOPinConfigure(GPIO_PB2_EPI0S27);
	GPIOPinTypeEPI(GPIO_PORTB_BASE, GPIO_PIN_2);

	// Enable pin PL4 for EPI0 EPI0S26
	GPIOPinConfigure(GPIO_PL4_EPI0S26);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_4);

	// Enable pin PK6 for EPI0 EPI0S25
	GPIOPinConfigure(GPIO_PK6_EPI0S25);
	GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_6);

	// Enable pin PK7 for EPI0 EPI0S24
	GPIOPinConfigure(GPIO_PK7_EPI0S24);
	GPIOPinTypeEPI(GPIO_PORTK_BASE, GPIO_PIN_7);

	// Enable pin PQ3 for EPI0 EPI0S23
	GPIOPinConfigure(GPIO_PQ3_EPI0S23);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_3);

	// Enable pin PQ2 for EPI0 EPI0S22
	GPIOPinConfigure(GPIO_PQ2_EPI0S22);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_2);

	// Enable pin PQ1 for EPI0 EPI0S21
	GPIOPinConfigure(GPIO_PQ1_EPI0S21);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_1);

	// Enable pin PQ0 for EPI0 EPI0S20
	GPIOPinConfigure(GPIO_PQ0_EPI0S20);
	GPIOPinTypeEPI(GPIO_PORTQ_BASE, GPIO_PIN_0);

	// Enable pin PL3 for EPI0 EPI0S19
	GPIOPinConfigure(GPIO_PL3_EPI0S19);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_3);

	// Enable pin PL2 for EPI0 EPI0S18
	GPIOPinConfigure(GPIO_PL2_EPI0S18);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_2);

	// Enable pin PL1 for EPI0 EPI0S17
	GPIOPinConfigure(GPIO_PL1_EPI0S17);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_1);

	// Enable pin PL0 for EPI0 EPI0S16
	GPIOPinConfigure(GPIO_PL0_EPI0S16);
	GPIOPinTypeEPI(GPIO_PORTL_BASE, GPIO_PIN_0);

	// Enable pin PM0 for EPI0 EPI0S15
	GPIOPinConfigure(GPIO_PM0_EPI0S15);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_0);

	// Enable pin PM1 for EPI0 EPI0S14
	GPIOPinConfigure(GPIO_PM1_EPI0S14);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_1);

	// Enable pin PM2 for EPI0 EPI0S13
	GPIOPinConfigure(GPIO_PM2_EPI0S13);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_2);

	// Enable pin PM3 for EPI0 EPI0S12
	GPIOPinConfigure(GPIO_PM3_EPI0S12);
	GPIOPinTypeEPI(GPIO_PORTM_BASE, GPIO_PIN_3);

	// Enable pin PG0 for EPI0 EPI0S11
	GPIOPinConfigure(GPIO_PG0_EPI0S11);
	GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_0);

	// Enable pin PG1 for EPI0 EPI0S10
	GPIOPinConfigure(GPIO_PG1_EPI0S10);
	GPIOPinTypeEPI(GPIO_PORTG_BASE, GPIO_PIN_1);

	// Enable pin PA7 for EPI0 EPI0S9
	GPIOPinConfigure(GPIO_PA7_EPI0S9);
	GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_7);

	// Enable pin PA6 for EPI0 EPI0S8
	GPIOPinConfigure(GPIO_PA6_EPI0S8);
	GPIOPinTypeEPI(GPIO_PORTA_BASE, GPIO_PIN_6);

	// Enable pin PC4 for EPI0 EPI0S7
	GPIOPinConfigure(GPIO_PC4_EPI0S7);
	GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_4);

	// Enable pin PC5 for EPI0 EPI0S6
	GPIOPinConfigure(GPIO_PC5_EPI0S6);
	GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_5);

	// Enable pin PC6 for EPI0 EPI0S5
	GPIOPinConfigure(GPIO_PC6_EPI0S5);
	GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_6);

	// Enable pin PC7 for EPI0 EPI0S4
	GPIOPinConfigure(GPIO_PC7_EPI0S4);
	GPIOPinTypeEPI(GPIO_PORTC_BASE, GPIO_PIN_7);

	// Enable pin PH3 for EPI0 EPI0S3
	GPIOPinConfigure(GPIO_PH3_EPI0S3);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_3);

	// Enable pin PH2 for EPI0 EPI0S2
	GPIOPinConfigure(GPIO_PH2_EPI0S2);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_2);

	// Enable pin PH1 for EPI0 EPI0S1
	GPIOPinConfigure(GPIO_PH1_EPI0S1);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_1);

	// Enable pin PH0 for EPI0 EPI0S0
	GPIOPinConfigure(GPIO_PH0_EPI0S0);
	GPIOPinTypeEPI(GPIO_PORTH_BASE, GPIO_PIN_0);

	// Set the EPI clock to one half of the system clock.
	EPIDividerSet(EPI0_BASE, 1);

	// Sets the usage mode of the EPI module.
	EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL);

	// Configure the mode.
	uint32_t Mode;
	Mode = EPI_GPMODE_CLKPIN | EPI_GPMODE_ASIZE_4 | EPI_GPMODE_DSIZE_24;
	EPIConfigGPModeSet(EPI0_BASE, Mode, 0, 0);

	// Set the address map.
	uint32_t Map =  EPI_ADDR_PER_BASE_A |EPI_ADDR_PER_SIZE_256B;
	EPIAddressMapSet(EPI0_BASE, Map);

	// Trigger on FIFO read buffer at 1/4 full or on Stall error.
	EPIFIFOConfig(EPI0_BASE, (EPI_FIFO_CONFIG_RX_1_4 | EPI_FIFO_CONFIG_RSTALLERR));

	// Interrupt on RX request, Error or DMA RX done
	//Mode = EPI_INT_RXREQ | EPI_INT_ERR | EPI_INT_DMA_RX_DONE;
	Mode = EPI_INT_ERR | EPI_INT_DMA_RX_DONE;
	EPIIntEnable(EPI0_BASE, Mode);

	// Wait for the EPI initialization to complete.
	while(HWREG(EPI0_BASE + EPI0_STAT_R) & EPI_STAT_INITSEQ) {};


	// Set the EPI memory pointer to the base of EPI memory space.  Note that
	// g_pui16EPISdram is declared as volatile so the compiler should not
	// optimize reads out of the memory.  With this pointer, the memory space
	// is accessed like a simple array.
	static volatile uint32_t *g_pui16EPISdram;
	g_pui16EPISdram = (uint32_t *)0xa0000000;

	volatile uint32_t v;

	// The register at address 7 is a write/read test register, so test it
	// Assume all tests pass unless proven otherwise
	bool Failed = false;

	g_pui16EPISdram[7] = 0x00000000;
	v = g_pui16EPISdram[7];
	//TCPLogWrite("     Wrote 00000000, Read %08XH", v);
	if (v != 0x00000000)
	Failed = true;

	g_pui16EPISdram[7] = 0x00ffffff;
	v = g_pui16EPISdram[7];
	//TCPLogWrite("     Wrote 00ffffff, Read %08XH", v);
	if (v != 0x00ffffff)
	Failed = true;

	// Shift a '1' through all bits to check for stuck bits
	uint32_t j;
	for (j = 0; j < 24; j++)
	{
	int32_t Val = 0x00000001 << j;
	g_pui16EPISdram[7] = Val;
	v = g_pui16EPISdram[7];
	//TCPLogWrite("     Wrote %08XH, Read %08XH", Val, v);
	if (v != Val)
	  Failed = true;
	}


	// Leave a final value
	g_pui16EPISdram[7] = 0x00ACEACE;
}

void initDma(void)
{
	  // Init DMA Stuff
	  SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);

	  // Enable it to run while processor is sleeping
	  SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA);

	  // Enable the DMA Controller for use
	  uDMAEnable();

	  // Setup the control table
	  uDMAControlBaseSet(dmaControlTable);

	  uDMAChannelAssign(UDMA_CH30_EPI0RX);

	  // Disable request mask
	  uDMAChannelAttributeDisable(UDMA_CH30_EPI0RX, UDMA_ATTR_ALTSELECT | UDMA_ATTR_REQMASK);

	  // Enable high priority and burst mode
	  uDMAChannelAttributeEnable(UDMA_CH30_EPI0RX, UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_USEBURST);

	  // Configuration
	  uDMAChannelControlSet(UDMA_CH30_EPI0RX | UDMA_PRI_SELECT,
			  	  	  	  	UDMA_SIZE_32 | UDMA_SRC_INC_32 |
	                        UDMA_DST_INC_32 | UDMA_ARB_8);

	  // Configure the parameters of the transfer
	  uDMAChannelTransferSet(UDMA_CH30_EPI0RX | UDMA_PRI_SELECT, UDMA_MODE_BASIC,
	                         (void*)0xA0000000, (void*) &g_pui8Buffer[g_TargetBufferIndex], 8);
}


void read(uint8_t* buffer, uint32_t size)
{
//    if(size > 0)
//    {
//		uDMAChannelTransferSet(UDMA_SEC_CHANNEL_EPI0RX, UDMA_MODE_BASIC,
//							  (void*)0xa0000000, (void*) buffer, size);
//		EPINonBlockingReadConfigure(EPI0_BASE, 0, EPI_NBCONFIG_SIZE_32, 0x00000000);
//		EPINonBlockingReadStart(EPI0_BASE, 0, size);
//		uDMAChannelEnable(UDMA_SEC_CHANNEL_EPI0RX);
//    }
}


void EPIIntHandler(void)
{
    uint32_t intStatus;
    uint32_t channelModeRX;

    g_EPIIntCount++;

    // Handle any EPI error IRQ signals.
    intStatus = EPIIntErrorStatus(EPI0_BASE);
    if(intStatus)
    {
        g_ui32EPIErrors++;
    }
    //EPI_INT_ERR_DMARDIC
    EPIIntErrorClear(EPI0_BASE, intStatus);


    intStatus = EPIIntStatus(EPI0_BASE, true);

    if(intStatus)
    {
        g_ui32EPIStatus = intStatus;
    }

    // Get any DMA related information. Clear the IRQ.
    intStatus = uDMAIntStatus();
    uDMAIntClear(intStatus);

    // Try to clear uDMA read complete interrupt (doesn't work)
    // Isn't there a TivaWare call to do this?
    HWREG(EPI0_BASE + EPI0_EISC_R) = 0x00000018;

    channelModeRX = uDMAChannelModeGet(UDMA_CH30_EPI0RX | UDMA_PRI_SELECT);

    if ((intStatus & 0x40000000) && (channelModeRX == UDMA_MODE_STOP))
    {
        g_ui32RxCount++;
        g_TargetBufferIndex += 8;
    }
}

int main()
{
    uint32_t ui32Loop, ui32TempRxCount;

    g_EPIIntCount = 0;
    g_TargetBufferIndex = 0;

    // Setup clocks
    uint32_t SysClockFreq = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
                                       SYSCTL_OSC_MAIN | SYSCTL_USE_PLL |
                                       SYSCTL_CFG_VCO_480), 120000000);

    // Set the device pinout appropriately for this board.
    PinoutSet();

    // Configure SysTick for a periodic interrupt.
    SysTickPeriodSet(SysClockFreq / 100);
    SysTickEnable();
    SysTickIntEnable();

    // Initialize RX DMA count and error count.
    g_ui32RxCount = 0;
    g_ui32DMAErrCount = 0;

    // Set the Global buffer to known values.
    memset(g_pui8Buffer, 0xaa, 1024 * 4);


    // Set Interrupt Priorities - Highest to lowest.
    // If not specified interrupt is highest priority
    IntPrioritySet(FAULT_SYSTICK, 0x00000000);
    IntPrioritySet(INT_EPI0,      0x00000010);
    IntPrioritySet(INT_UDMA,      0x00000020);
    IntPrioritySet(INT_UDMAERR,   0x00000030);

    // Initialize EPI & uDMA
    initDma();
    initEpi();

	// Clear all pending interrupts
	uDMAIntClear(uDMAIntStatus());
	EPIIntErrorClear(EPI0_BASE, EPIIntErrorStatus(EPI0_BASE));
	EPIIntErrorClear(EPI0_BASE, 0xffffffff);


	// Enable the applicable interrupts
	IntEnable(INT_UDMA);
	IntEnable(INT_UDMAERR);
	IntEnable(INT_EPI0);

    IntMasterEnable();



    // Do it
    uDMAChannelEnable(UDMA_CH30_EPI0RX);

    // Configure a non-blocking read transfer: Ch 0, 32-bit data, address 0
    EPINonBlockingReadConfigure(EPI0_BASE, 0, EPI_NBCONFIG_SIZE_32, 0x00000000);

    // Starts a read transaction - 8 32-bit data values are put into the NBR FIFO
    EPINonBlockingReadStart(EPI0_BASE, 0, 8);

    // Look at data in FIFO
    uint32_t FIFOData[16];
    memset(FIFOData, 0xa5, 64);
    uint32_t Count = EPINonBlockingReadGet32(EPI0_BASE, 8, FIFOData);

    uint32_t x = 0;
	while(1)
	{
		x++;
	}




//
//    ui32Loop = 0;
//    while(1)
//    {
//        ui32TempRxCount = g_ui32RxCount;
//        read(g_pui8Buffer, 8);
//
//        //
//        // Wait for the DMA to complete
//        //
//        while(g_ui32RxCount <= ui32TempRxCount)
//        {
////            if(g_ui32DMAErrCount)
////            {
////                UARTprintf("DMA error count = %d\n", g_ui32DMAErrCount);
////            }
////            if(g_ui32EPIErrors)
////            {
////                UARTprintf("EPI error count = %d\n", g_ui32EPIErrors);
////            }
//        }
//
//        ui32Loop++;
//
//		//
//		// Arbitrary count selected. Halt the loop and output some data.
//		//
//		if(ui32Loop > 2000)
//		{
//			for(ui32Loop = 1; ui32Loop <= 256; ui32Loop++)
//			{
//				if(!(ui32Loop % 12))
//				{
//					//UARTprintf("\n%04d:", (ui32Loop - 1));
//				}
//			}
//
//			//
//			// Spin.
//			//
//			while(1)
//			{
//			}
//		}
//    }
}

0 Amit Ashara over 9 years ago in reply to Jeff McDevitt

TI__Guru**** 244400 points

Hello Jeff,

Since your code seems to be using an SDRAM, can you please try the attached code? (I think I got it working)

ektm4c129_sdram_udma.zip

Regards

Amit

0 Jeff McDevitt over 9 years ago in reply to Amit Ashara

Expert 1775 points

Amit,

I am not sure why you think I am using an SDRAM. I am using an FPGA so teh EPI is in GP Mode. Regardless, your example had the code I was looking for:

// If only the RX DMA Done Interrupt bit is set then clear it and set the
// transfer done flag to true
if (intStatus)
{
g_ui32EPIStatus = intStatus;

if (intStatus == EPI_INT_DMA_RX_DONE)
{
EPIIntErrorClear(EPI0_BASE, EPI_INT_ERR_DMARDIC);
g_bEPITransferComplete = true;
}
}

Thanks!

0 Amit Ashara over 9 years ago in reply to Jeff McDevitt

TI__Guru**** 244400 points

Hello Jeff

This line is required for SDRAM initialization....

while(HWREG(EPI0_BASE + EPI0_STAT_R) & EPI_STAT_INITSEQ) {};

Regards
Amit

0 Jeff McDevitt over 9 years ago in reply to Amit Ashara

Expert 1775 points

Amit,

I removed that line.

The problem that I am seeing now is very strange. It the EPI Interrupt handler I attempt to clear the EPI_INT_DMA_RX_DONE interrupt. I then read the interrupt status again and it is not cleared, unless I have the EPI registers open for viewing. I have tested this on the DK-TM4C129X kit. Hopefully you have access to one of these so you can test this.

Thanks,EPITest.zip

Jeff

0 Amit Ashara over 9 years ago in reply to Jeff McDevitt

TI__Guru**** 244400 points

Hello Jeff,

The issue in the code is the manner in which you are programming the uDMA and the reading mechanism of EPI's NBR. The uDMA is reading from 0xA000.0000 and not the NBR FIFO. Hence the issue of the Interrupt not clearing. When you open the Register view, you may have inadvertently had the FIFO read register head open, which caused the debugger to read the FIFO and thus allowing the interrupt to get cleared. I have attached your project with some changes, that you may diff.

7532.EPITest.zip

Regards

Amit

0 Jeff McDevitt over 9 years ago in reply to Amit Ashara

Expert 1775 points

Amit,

That was it! Thanks for your help (and patience).

Jeff

0 Amit Ashara over 9 years ago in reply to Jeff McDevitt

TI__Guru**** 244400 points

Hello Jeff

All in a day's work. Glad it is working for you.

Regards
Amit

Arm-based microcontrollers

Arm-based microcontrollers forum

A question about EPI uDMA interrupts