TM4C1292 -Ethernet Switch.(Data loss in ethernet).

Krishnan G Nair

Other Parts Discussed in Thread: TM4C1292NCPDT

Hello,

We are using TM4C1292 Microcontroller. We.We are receving data from external world to the controller via Micreal Ethernet switch,Switch 3rd port is connected to controller and 1 and 2nd ports to external world.

The problem is if 100 packets of 1 sec delay and 1k size is given to controller its losing 10-20% of packets.The rate of loss is random (10-20 ) packets per 100.

How we tested is if we connect 2 external ports of switch to 2 different pc and done the test there is no loss of data.But if we send from port 1 to controller via port 3 of switch we are loosing data.

When ever controller receives Ethernet data we are toggling a led via GPO.

//*****************************************************************//

#include "CTI_NODE1_4_COMMONINC.h"

#include "inc/tm4c1292ncpdt.h"

#include "CTI_NODE1_4_EPI_MANAGER.h"

#include "CTI_Switch.h"

//******************************************************************//

// Defines for setting up the system clock.

//*******************************************************************//

#define CLOCK_CONF_SECOND 100

#define SYSTICKHZ CLOCK_CONF_SECOND

#define SYSTICKMS (1000 / SYSTICKHZ)

#define SYSTICKUS (1000000 / SYSTICKHZ)

#define SYSTICKNS (1000000000 / SYSTICKHZ)

//*****************************************************************************

// Macro for accessing the Ethernet header information in the buffer.

//*****************************************************************************

//u8_t g_pui8UIPBuffer[4200];

typedef unsigned char u8_t;

#define BUF ((struct uip_eth_hdr *)uip_buf)

#define CONSTCHECKSUM 0x7001

#define UDP_SPORT1 0xC3

#define UDP_SPORT2 0x52

#define UDP_DPORT1 0xD6

#define UDP_DPORT2 0xDA

#define MAC1 0x01

#define MAC2 0x02

#define MAC3 0x03

#define MAC4 0x01

#define MAC5 0x02

#define MAC6 0x03

#define MAC11 0xFF

#define MAC12 0xFF

#define MAC13 0xFF

#define MAC14 0xFF

#define MAC15 0xFF

#define MAC16 0xFF

//*****************************************************************************

// Ethernet DMA descriptors.

// Although uIP uses a single buffer, the MAC hardware needs a minimum of

// 3 receive descriptors to operate.

//*****************************************************************************

#define NUM_TX_DESCRIPTORS 3

#define NUM_RX_DESCRIPTORS 3

tEMACDMADescriptor g_psRxDescriptor[NUM_TX_DESCRIPTORS];

tEMACDMADescriptor g_psTxDescriptor[NUM_RX_DESCRIPTORS];

//----------------------------------------------------------------------

extern int smi_read(unsigned char Reg, unsigned char *readData);

extern int smi_write ( unsigned char Reg,unsigned char Data);

//****************************************************************************

uint32_t g_ui32RxDescIndex;

uint32_t g_ui32TxDescIndex;

//****************************************************************************

int a,b,c;

int c = 0;

int d = 0;

int h = 0;

unsigned short cnt = 0000;

unsigned char *cptr = NULL;

unsigned short *sram =NULL;

int loopp;

//******************************************************************************

int size = 0, index = 0;

unsigned short Buffer[10000];

unsigned short tmpVal = 0;

char j,k;

int qwl=0;

#define FPGA_START_ADDRESS 0x000000

#define FPGA_END_ADDRESS 0x3FFFFF

//*****************************************************************************

// Transmit and receive buffers.

//*****************************************************************************

#define RX_BUFFER_SIZE 1150

#define TX_BUFFER_SIZE 1150

uint8_t g_pui8RxBuffer[RX_BUFFER_SIZE];

uint8_t g_pui8TxBuffer[TX_BUFFER_SIZE];

char test[100];

u8_t *uip_buf = g_pui8TxBuffer;

uint32_t ui32CCConfig;

int packetreceive=0;

//*****************************************************************************

// A set of flags. The flag bits are defined as follows:

// 0 -> An indicator that a SysTick interrupt has occurred.

// 1 -> An RX Packet has been received.

// 2 -> A TX packet DMA transfer is pending.

// 3 -> A RX packet DMA transfer is pending.

//*****************************************************************************

#define FLAG_SYSTICK 0

#define FLAG_RXPKT 1

#define FLAG_TXPKT 2

#define FLAG_RXPKTPEND 3

static volatile uint32_t g_ui32Flags;

extern unsigned long CTI_READ_TEMPSENSOR(void);

extern void CTI_CONFIG_TEMPSENSOR();

//*****************************************************************************

struct uip_etth_addr {

u8_t addr[6];

};

//*****************************************************************************

// A system tick counter, incremented every SYSTICKMS.

//*****************************************************************************

volatile uint32_t g_ui32TickCounter = 0;

//*****************************************************************************

// The error routine that is called if the driver library encounters an error.

//*****************************************************************************

void __error__(char *pcFilename, uint32_t ui32Line) {

}

//*****************************************************************************

// The interrupt handler for the SysTick interrupt.

//*****************************************************************************

void SysTickIntHandler(void) {

// Increment the system tick count.

g_ui32TickCounter++;

// Indicate that a SysTick interrupt has occurred.

HWREGBITW(&g_ui32Flags, FLAG_SYSTICK) = 1;

}

//*****************************************************************************

// The interrupt handler for the Ethernet interrupt.

//*****************************************************************************

void EthernetIntHandler(void) {

uint32_t ui32Temp;

// Read and Clear the interrupt.

ui32Temp = EMACIntStatus(EMAC0_BASE, true);

EMACIntClear(EMAC0_BASE, ui32Temp);

// Check to see if an RX Interrupt has occurred.

if (ui32Temp & EMAC_INT_RECEIVE) {

// Indicate that a packet has been received.

HWREGBITW(&g_ui32Flags, FLAG_RXPKT) = 1;

}

// Has the DMA finished transferring a packet to the transmitter?

if (ui32Temp & EMAC_INT_TRANSMIT) {

// Indicate that a packet has been sent.

HWREGBITW(&g_ui32Flags, FLAG_TXPKT) = 0;

}

//*****************************************************************************

// Read a packet from the DMA receive buffer into the uIP packet buffer.

//*****************************************************************************

int32_t PacketReceive(uint32_t ui32Base, uint8_t *pui8Buf, int32_t i32BufLen) {

int_fast32_t i32FrameLen, i32Loop;

packetreceive++;

// Check the arguments.

ASSERT(ui32Base == EMAC0_BASE); ASSERT(pui8Buf != 0); ASSERT(i32BufLen > 0);

// By default, we assume we got a bad frame.

i32FrameLen = 0;

// Make sure that we own the receive descriptor.

if (!(g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus & DES0_RX_CTRL_OWN)) {

// We own the receive descriptor so check to see if it contains a valid

// frame. Look for a descriptor error, indicating that the incoming

// packet was truncated or, if this is the last frame in a packet,

// the receive error bit.

if (!(g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus &

DES0_RX_STAT_ERR)) {

// We have a valid frame so copy the content to the supplied

// buffer. First check that the "last descriptor" flag is set. We

// sized the receive buffer such that it can always hold a valid

// frame so this flag should never be clear at this point but...

if (g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus &

DES0_RX_STAT_LAST_DESC) {

i32FrameLen =

((g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus &

DES0_RX_STAT_FRAME_LENGTH_M) >>

DES0_RX_STAT_FRAME_LENGTH_S);

// Sanity check. This shouldn't be required since we sized the

// uIP buffer such that it's the same size as the DMA receive

// buffer but, just in case...

if (i32FrameLen > i32BufLen) {

i32FrameLen = i32BufLen;

}

// Copy the data from the DMA receive buffer into the provided

// frame buffer.

int i = 0;

/*for (i32Loop = 43; i32Loop < 50i32FrameLen; i32Loop++, i++) {

test[i] = g_pui8RxBuffer[i32Loop];

}*/

}

// Move on to the next descriptor in the chain.

g_ui32RxDescIndex++;

if (g_ui32RxDescIndex == NUM_RX_DESCRIPTORS) {

g_ui32RxDescIndex = 0;

}

// Mark the next descriptor in the ring as available for the receiver

// to write into.

g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus = DES0_RX_CTRL_OWN;

}

// Return the Frame Length

return (i32FrameLen);

}

//*****************************************************************************

// Transmit a packet from the supplied buffer.

//*****************************************************************************

static int32_t PacketTransmit(uint32_t ui32Base, uint8_t *pui8Buf,int32_t i32BufLen) {

uint32_t i32Loop;

// Indicate that a packet is being sent.

HWREGBITW(&g_ui32Flags, FLAG_TXPKT) = 1;

// Check that we're not going to overflow the transmit buffer. This

// shouldn't be necessary since the uIP buffer is smaller than our DMA

// transmit buffer but, just in case...

if (i32BufLen > TX_BUFFER_SIZE) {

i32BufLen = TX_BUFFER_SIZE;

}

/*for(i32Loop = 0; i32Loop < i32BufLen; i32Loop++)

{

g_pui8TxBuffer[i32Loop] = pui8Buf[i32Loop];

}

// Move to the next descriptor.

g_ui32TxDescIndex++;

if (g_ui32TxDescIndex == NUM_TX_DESCRIPTORS) {

g_ui32TxDescIndex = 0;

}

// Fill in the packet size and tell the transmitter to start work.

g_psTxDescriptor[g_ui32TxDescIndex].ui32Count = (uint32_t) i32BufLen;

g_psTxDescriptor[g_ui32TxDescIndex].ui32CtrlStatus = (DES0_TX_CTRL_LAST_SEG

| DES0_TX_CTRL_FIRST_SEG |

DES0_TX_CTRL_INTERRUPT | DES0_TX_CTRL_IP_ALL_CKHSUMS |

DES0_TX_CTRL_CHAINED | DES0_TX_CTRL_OWN);

// Tell the DMA to reacquire the descriptor now that we've filled it in.

EMACTxDMAPollDemand(EMAC0_BASE);

// Return the number of bytes sent.

return (i32BufLen);

}

//*****************************************************************************

// Initialize the transmit and receive DMA descriptors. We apparently need

// a minimum of 3 descriptors in each chain. This is overkill since uIP uses

// a single, common transmit and receive buffer so we tag each descriptor

// with the same buffer and will make sure we only hand the DMA one descriptor

// at a time.

//*****************************************************************************

void InitDescriptors(uint32_t ui32Base) {

uint32_t ui32Loop;

// Initialize each of the transmit descriptors. Note that we leave the OWN

// bit clear here since we have not set up any transmissions yet.

for (ui32Loop = 0; ui32Loop < NUM_TX_DESCRIPTORS; ui32Loop++) {

g_psTxDescriptor[ui32Loop].ui32Count = (DES1_TX_CTRL_SADDR_INSERT

| (TX_BUFFER_SIZE << DES1_TX_CTRL_BUFF1_SIZE_S));

g_psTxDescriptor[ui32Loop].pvBuffer1 = g_pui8TxBuffer;

g_psTxDescriptor[ui32Loop].DES3.pLink =

(ui32Loop == (NUM_TX_DESCRIPTORS - 1)) ?

g_psTxDescriptor : &g_psTxDescriptor[ui32Loop + 1];

g_psTxDescriptor[ui32Loop].ui32CtrlStatus = (DES0_TX_CTRL_LAST_SEG

| DES0_TX_CTRL_FIRST_SEG |

DES0_TX_CTRL_INTERRUPT | DES0_TX_CTRL_CHAINED |

DES0_TX_CTRL_IP_ALL_CKHSUMS);

}

// Initialize each of the receive descriptors. We clear the OWN bit here

// to make sure that the receiver doesn't start writing anything

// immediately.

for (ui32Loop = 0; ui32Loop < NUM_RX_DESCRIPTORS; ui32Loop++) {

g_psRxDescriptor[ui32Loop].ui32CtrlStatus = 0;

g_psRxDescriptor[ui32Loop].ui32Count = (DES1_RX_CTRL_CHAINED

| (RX_BUFFER_SIZE << DES1_RX_CTRL_BUFF1_SIZE_S));

g_psRxDescriptor[ui32Loop].pvBuffer1 = g_pui8RxBuffer;

g_psRxDescriptor[ui32Loop].DES3.pLink =

(ui32Loop == (NUM_RX_DESCRIPTORS - 1)) ?

g_psRxDescriptor : &g_psRxDescriptor[ui32Loop + 1];

}

// Set the descriptor pointers in the hardware.

EMACRxDMADescriptorListSet(ui32Base, g_psRxDescriptor);

EMACTxDMADescriptorListSet(ui32Base, g_psTxDescriptor);

// Start from the beginning of both descriptor chains. We actually set

// the transmit descriptor index to the last descriptor in the chain

// since it will be incremented before use and this means the first

// transmission we perform will use the correct descriptor.

g_ui32RxDescIndex = 0;

g_ui32TxDescIndex = NUM_TX_DESCRIPTORS - 1;

}

Configure_gpiopins_for_RMII()

{

//-----Alternate GPIO pin Selection for RMII--------//

GPIOPinConfigure(GPIO_PG3_EN0TXEN);

GPIOPinConfigure(GPIO_PG5_EN0TXD1);

GPIOPinConfigure(GPIO_PG4_EN0TXD0);

GPIOPinConfigure(GPIO_PG7_EN0RXDV);

GPIOPinConfigure(GPIO_PQ5_EN0RXD0);

GPIOPinConfigure(GPIO_PQ6_EN0RXD1);

GPIOPinConfigure(GPIO_PK4_EN0INTRN);

//GPIOPinConfigure(GPIO_PF2_EN0MDC);

//GPIOPinConfigure(GPIO_PF3_EN0MDIO);

GPIOPinConfigure(GPIO_PM4_EN0RREF_CLK);

//------------GPIO ETHERNET PIN CONFIGURATION---//

GPIOPinTypeEthernetMII(GPIO_PORTG_BASE,0xB8);

GPIOPinTypeEthernetMII(GPIO_PORTQ_BASE,0x60);

GPIOPinTypeEthernetMII(GPIO_PORTK_BASE,0x10);

//GPIOPinTypeEthernetMII(GPIO_PORTF_BASE,0x0C);

GPIOPinTypeEthernetMII(GPIO_PORTM_BASE,0x10);

GPIOPadConfigSet (GPIO_PORTG_BASE, 0xB8, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);

GPIOPadConfigSet (GPIO_PORTQ_BASE, 0x60, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);

//GPIOPadConfigSet (GPIO_PORTF_BASE, 0x0C, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);

GPIOPadConfigSet (GPIO_PORTK_BASE, 0x10, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);

GPIOPadConfigSet (GPIO_PORTM_BASE, 0x10, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);

GPIODirModeSet (GPIO_PORTG_BASE, 0xB8, GPIO_DIR_MODE_HW);

GPIODirModeSet (GPIO_PORTQ_BASE, 0x60, GPIO_DIR_MODE_HW);

//GPIODirModeSet (GPIO_PORTF_BASE, 0x0C, GPIO_DIR_MODE_HW);

GPIODirModeSet (GPIO_PORTK_BASE, 0x10, GPIO_DIR_MODE_HW);

GPIODirModeSet (GPIO_PORTM_BASE, 0x10, GPIO_DIR_MODE_HW);

}

//*****************************************************************************

// This example demonstrates the use of the Ethernet Controller with the uIP

// TCP/IP stack.

//*****************************************************************************

int main(void) {

static struct uip_etth_addr sTempAddr;

int32_t i32PeriodicTimer =0, i32ARPTimer = 0,numofbytes=0;

uint32_t ui32PHYConfig;

uint16_t ui16Val;

uint8_t ui8PHYAddr;

uint16_t add,reed=0 ;

unsigned long Data=0;

unsigned char readData=0;

sram =(unsigned short *)0x20000500;

int ll,ii=0,j=0;

unsigned char DipSWVal;

// Run from the PLL at 120 MHz.Setting System Clock to 120 Mhz.

ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |

SYSCTL_OSC_MAIN |

SYSCTL_USE_PLL |

SYSCTL_CFG_VCO_480), 120000000);

// Configure the device pins.

CTI__GPIO_Bank();

GPIOPinTypeGPIOOutput(GPIO_PORTN_BASE, GPIO_PIN_3);

GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_3, 0);

GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_2);

GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_3);

//*******************************fUNCTIONS ADDRED FOR epi,interrupt***************************//

CTI_Disable_UnsedDev();

//**********************External PHY Configuration********************************************//

ui32PHYConfig = EMAC_PHY_TYPE_EXTERNAL_RMII;

ui8PHYAddr = 0x02;

//** MAC address to program the hardware registers, then program the MAC address into the Ethernet Controller registers**//

sTempAddr.addr[0] = 0x01;

sTempAddr.addr[1] = 0x02;

sTempAddr.addr[2] = 0x03;

sTempAddr.addr[3] = 0x01;

sTempAddr.addr[4] = 0x02;

sTempAddr.addr[5] = 0x03;

//---------------------------------------SMI-------------------------//

//---------------------------------------------------------------------------//

Configure_gpiopins_for_RMII();

// Configure SysTick for a periodic interrupt.

SysTickPeriodSet(ui32SysClock / SYSTICKHZ);

SysTickEnable();

SysTickIntEnable();

// Enable and reset the Ethernet modules.

SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0);

SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0);

// Wait for the MAC to be ready.

//UpdateStatus("Waiting for MAC to be ready...");

while (!SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0))

{

}

// Configure for use with the External PHY.

EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_TYPE_EXTERNAL_RMII );

while (!SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0))

{

}

//UpdateStatus("MAC ready.");

//-----------------------------------------------------------------//

// Reset the MAC.

EMACReset(EMAC0_BASE);

//----------------------emac RMII clock config-------------//

HWREG(EMAC0_BASE + EMAC_O_CC) |= (EMAC_CC_CLKEN);

SysCtlDelay(100);

HWREG(EMAC0_BASE +EMAC_O_DMABUSMOD) |=(EMAC_DMABUSMOD_SWR);

SysCtlDelay(100);

// Initialize the MAC and set the DMA mode.

//-----------------------------------------------------//

EMACInit(EMAC0_BASE, ui32SysClock,

EMAC_BCONFIG_TX_PRIORITY | EMAC_BCONFIG_MIXED_BURST |

EMAC_BCONFIG_DMA_PRIO_WEIGHT_2 | EMAC_BCONFIG_PRIORITY_2_1,8, 8, 0);

EMACConfigSet(EMAC0_BASE,

(( EMAC_CONFIG_100MBPS)|

EMAC_CONFIG_FULL_DUPLEX |

EMAC_CONFIG_CHECKSUM_OFFLOAD |

EMAC_CONFIG_7BYTE_PREAMBLE |

EMAC_CONFIG_IF_GAP_96BITS | EMAC_CONFIG_USE_MACADDR0 |

EMAC_CONFIG_SA_FROM_DESCRIPTOR |

EMAC_CONFIG_BO_LIMIT_1024),

(EMAC_MODE_RX_STORE_FORWARD |

EMAC_MODE_TX_STORE_FORWARD |

EMAC_MODE_TX_THRESHOLD_64_BYTES |

EMAC_MODE_RX_THRESHOLD_64_BYTES), 0);

// Initialize the Ethernet DMA descriptors.

InitDescriptors(EMAC0_BASE);

// Program the hardware with its MAC address (for filtering).

EMACAddrSet(EMAC0_BASE, 0, (uint8_t *) &sTempAddr);

// Set MAC filtering options. We receive all broadcast and multicast

// packets along with those addressed specifically for us.

MAP_EMACFrameFilterSet(EMAC0_BASE, (EMAC_FRMFILTER_SADDR |

EMAC_FRMFILTER_PASS_MULTICAST |

EMAC_FRMFILTER_PASS_NO_CTRL));

// Clear any pending interrupts.

EMACIntClear(EMAC0_BASE, EMACIntStatus(EMAC0_BASE, false));

// Enable the Ethernet MAC transmitter and receiver.

EMACTxEnable(EMAC0_BASE);

EMACRxEnable(EMAC0_BASE);

// Enable the Ethernet interrupt.

IntEnable(INT_EMAC0);

// Enable the Ethernet RX Packet interrupt source.

EMACIntEnable(EMAC0_BASE, EMAC_INT_RECEIVE);

// Mark the first receive descriptor as available to the DMA to start

// the receive processing.

g_psRxDescriptor[g_ui32RxDescIndex].ui32CtrlStatus |= DES0_RX_CTRL_OWN;

// Enable Tx interrupt source

EMACIntEnable(EMAC0_BASE,EMAC_INT_TRANSMIT );

IntMasterEnable();

SysCtlDelay(100000000);

for(ii=0;ii<=250;ii++)

{

j++;

SysCtlDelay(1000);

epiReadData((short*) (uip_buf + 42));

SysCtlDelay(100);

numofbytes = PacketTransmit(EMAC0_BASE, uip_buf, 11068); //1068

}

i32ARPTimer = 0;

// Main Application Loop .

while (true) {

// Wait for an event to occur. This can be either a System Tick event,

// or an RX Packet event.

while(!g_ui32Flags)

{

}

// If SysTick, Clear the SysTick interrupt flag and increment the

// timers.

if(HWREGBITW(&g_ui32Flags, FLAG_SYSTICK) == 1)

{

HWREGBITW(&g_ui32Flags, FLAG_SYSTICK) = 0;

i32PeriodicTimer += SYSTICKMS;

i32ARPTimer += SYSTICKMS;

}

if (HWREGBITW(&g_ui32Flags, FLAG_RXPKT)) {

// Clear the RX Packet event flag.

HWREGBITW(&g_ui32Flags, FLAG_RXPKT) = 0;

//PacketReceive(EMAC0_BASE, uip_buf, 1100);

PacketReceive(EMAC0_BASE,g_pui8RxBuffer, 1100);

}

Any suggestions please,

Thanks in advance.

Regards,

Krishnan

over 9 years ago

0 Sai Reddy over 9 years ago

TI__Mastermind 22640 points

Hello Krishnan,

It is really hard to read/understand the code without "Syntaxhighlighter". For future reference, please use "Syntaxhighlighter" while posting code.

I am not clear when you say 1 sec delay. Is the delay after a burst of 100 packets?

Are you using raw Ethernet frames or TCP/IP packets for your test? Better to use raw frames (with dummy data) as TCP/IP will try to resend data if the transmission was not successful.

Since you are using a TM4C1292 based MCU, I assume you are using an external PHY. To eliminate the external PHY as the cause of this issue, can you try running the same experiment using a TI development board instead of your custom board. Alternatively, there are some MAC management counters and flags that keep a track of the good and bad frames. They start from offset 0x100. You can inspect these packets after each burst of data to see if the errors match.

Hope this helps!

Thanks,
Sai

0 Krishnan G Nair over 9 years ago in reply to Sai Reddy

Expert 1235 points

Sir,

I sec delay means time difference between 2 Ethernet packets .

We are using Raw ethernet frames(Raw packets +buffer).

Right now development kit is not available with us.

The controller mac is connected to Externel switch 3rd port.

We are handling ethernet data by transmit and receive interrupt.

I am attaching a sample diagram .We can receive and transmit packet no issue but the problem is with (10-20)% data loss.I will see the flags and MAC management counters as you mentionedDoc4.docx

0 Sai Reddy over 9 years ago in reply to Krishnan G Nair

TI__Mastermind 22640 points

Hello Krishnan,

In the diagram, the TM4C1292 Ethernet MAC is directly connected to the Micreal Switch using RMII. Does this mean that the Ethernt PHY is present on the Micreal Switch?

If the delay between each Ethernet Packet is 1 second, then my first suspect will be the PHY. It will be good to confirm this by running the same test on a TI development board using the internal PHY. Looking at the MAC management counters might provide some help.

Also are you capturing a Wireshark log? If not, it might be useful to use Wireshark to capture data going in and out of the PHY, to remove all other unknowns.

Thanks,
Sai

0 Djedjica over 9 years ago in reply to Sai Reddy

Intellectual 870 points

Hello everyone,
I've been researching for my project and bump into this post, just one quick question.
I will be using the same MCU and is going to be connected to the Micrel KSZ8873 switch over MII. Configuration for TM4C is similar as in this post
Configure_gpiopins_for_RMII() ??
Of course, pins set up for MII operation. Is that OK? There is very little documentation for this EMAC_PHY_TYPE_EXTERNAL_MII so I'm asking just to have some starting point.

Thank you.
Kind regards,
Djedjica

0 Krishnan G Nair over 9 years ago in reply to Djedjica

Expert 1235 points

Actually,

MMI-----------Interface for configuring switch registers

RMII signals to configure phy and tx,rx,control between swich and phy.

From my point of view your configuration is ok with limited understanding on your question.

But to configure switch registers check wether mii is enough or smi is required.

Smi is required means things will get difficult.

Regards,

Krishnan

91-9500087341

0 Djedjica over 9 years ago in reply to Krishnan G Nair

Intellectual 870 points

Hello Krishnan,
thank you for your response, I'm sorry if I get bit unclear, I was just thinking on using similar configuration as yours but instead RMII use MII to connect switch port to MCU, so I would configure those pins too
for example, pins that are not used for RMII
...
GPIOPinConfigure(GPIO_PK6_EN0TXD2); //transmit data 2
GPIOPinConfigure(GPIO_PK7_EN0TXD3); //transmit data 3
...

, and for begining keep Micrel switch in default configuration just to se if I can get frames in and out, so your post could be great starting point for me.
Kind regards,
Djedjica

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TM4C1292 -Ethernet Switch.(Data loss in ethernet).