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Difficulty getting eCAP4 & 5 working on TMS570LC4357 development kit

Other Parts Discussed in Thread: HALCOGEN

Hi All,

Both eCAP4 & eCAP5 are enabled and being driving be PWM modules, only the eCAP4 interrupt request is serviced. If I place a breakpoint in the ecap5Interrupt() it will never be reached. I can see in the registers that the IRQ flags are set for the eCAP5 module.

I have tested both the eCAP4 & eCAP5 modules independently and they work fine, it is just when we are using both that this problem seems to occur.

Here is the link to the previous post:

Thanks - Warren

  • Hi Warren,
    Is it possible that eCAP4 is constantly capturing a shorter input than eCAP5? Since the the eCAP4 input is short, it generates an interrupt more frequently than the eCAP5 interrupt. By default, eCAP4 has higher interrupt priority than eCAP5 and hence eCAP4 interrupt is constantly being served by the CPU. The higher priority eCAP4 kind of preempt the eCAP5 from being served.

    If you keep both eCAP4 and eCAP5 working but only to disable the eCAP4 interrupt mask in the VIM module, do you now see eCAP5 being served?
  • Hi Charles,

    I tested quite a few things here:

    If I disable CAP4 interrupts, CAP5 interrupts work just fine. If I input different frequencies, say 40 kHz to CAP5, and 20 kHz to CAP4, only CAP4 gets serviced. If I alternate disabling CAP4 interrupts, servicing CAP5, and then disabling CAP5 interrupts and re-enabling CAP4 interrupts both get serviced however CAP4 will get serviced 2 times for every 1 CAP5 interrupt serviced.

    I have not tried masking CAP4 in the VIM module so I will try that.

    - Warren

  • Hi Warren,
    Can you also check if the interrupt flag is cleared for eCAP4 after the CPU services the ISR? I'm thinking if the flag is not cleared for eCAP4 then it will keep re-entering eCAP4 ISR as soon as it exits the ISR.
  • Charles,

    Sure thing. Hopefully I will be able to get to it this afternoon and get you an answer.

    - warren
  • HI Charles,

    So ran some tests this morning, it looks to me like the eCAP4 interrupt request flag never gets cleared.. the following code is generated by HalCoGen:

    void ecap4Interrupt(void)
    {
        uint16 Int_Flag = ecapREG4->ECFLG & ecapREG4->ECEINT;
    
    /* USER CODE BEGIN (8) */
    /* USER CODE END */
    
        /* Clear Events, */
        /* Note : Current Implementation clears multiple all events set
           before this point, User notification function is called with Flags and user must take care of handling */    
        ecapREG4->ECCLR = Int_Flag;
        
        /* Clears the interrupt flag and enables further interrupts to be generated
           if an event flags is set to 1. */
        ecapREG4->ECCLR = 1U;
        
        /* Passing the Interrupt Flag to the user Notification Function */
        ecapNotification(ecapREG4,Int_Flag);
    
    /* USER CODE BEGIN (9) */
    /* USER CODE END */
    
    }

    When setting the ecapREG4->ECCLR register to the set interrupt flags to clear, the ECCLR register never changes, and the ECFLG register never clears the flags that the ECCLR register should clear.

    - Warren

  • Hi Warren,

      How did you know that the flag is not getting cleared? Are you using the debugger to single step through the code and find that the flag is not cleared after stepping through the code? If this is the case I think the reason is that the eCAP is in a free run mode. When the CPU is halted by the debugger the eCAP continues to run. Since your input comes in at 20kHz, as soon as you clear the flag it is getting set again. The frequency of setting the flag is much faster and frequent than you clearing it while single stepping. 

      I also created a simple test with both eCAP4 and eCAP5 running. However, I use both eCAPs to generate a simple PWM. eCAP4 generates a PWM 5x faster than the eCAP5. I create a global variable in each ISR to count the number of times the ISR is entered. I let it run for a while. I do see the count in eCAP4 to be 5x more than eCAP5. Nonetheless, both eCAP ISRs are entered unlike your original description where you said the eCAP5 ISR was never entered. 

      Please see attached project. 6232.LC4357_eCAP4_eCAP5_interrupt.zip

      

  • Charles,

    I implemented your example and everything works fine. I incrementally changed it to be exactly like our code. The only difference between your working example, and my non working example is now the printf() statements used in the eCAP example to print the period in ns to the console. Once I removed the printf() statements from my example code mine worked just fine.

    Any thoughts as to why printf() broke my example project?

    - Warren

  • Hi Warren,

    I don't really know why it does not work with the printf(). Please note that the printf() functions requires more than 400 bytes of stack. Perhaps you want to increase the stack size and try to see if it makes a difference.

    printf() is a type of C IO function which is funneled through very low-level functions which eventually reach one of two required two breakpoints, at label C$$IO$$ or C$$EXIT. The debugger watches for one of these breakpoints to be reached, at which point the debugger performs an I/O request for the program. As I mentioned in the earlier thread, once a breakpoint is reached the CPU is halted but the eCAP is continuing to generate interrupts when it detects the event. I suspect the setting of the flags is much faster than clearing the flags in the ISR due to the printf().
  • Hi Charles,

    That makes sense, I didn't know printf() used break points to print out data. I just assumed it pushed whatever is passed to it into the default UART module that is set up for debug communications with the host computer.

    Well either way, it looks like we are in business now, so thank you for helping us get through this issue!

    - Warren
  • Hi Warren,
    Glad your problem is resolved.