• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 30 subscribers
  • Views 782 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

About PLL

Chao Huo
Prodigy 30 points
Other Parts Discussed in Thread: TM4C123GH6PM

Hi all,

In the datasheet of tm4c123gh6pm, page 221, Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field.

SYSDIV         Divisor            Frequency(BYPASS=0)          Frequency (BYPASS=1)                       TivaWare™ Parametera

0x2                   /3                    66.67 MHz                                 Clock source frequency/3                     SYSCTL_SYSDIV_3
0x3                   /4                    50 MHz                                        Clock source frequency/4                     SYSCTL_SYSDIV_4

i dont understand how 66.67MHZ is calculated.

I mean, the out put frequency from VCO should be the same as input reference frequency(that is what PLL does). So, the value field where these 66,67 and 50 stands should depend on the input reference frequency. So it would be X/3 or X/4, not 400MHZ/3 nor 400MHZ/4.

Can anyone help to explain?

Thanks.

  • 0
    TI__Guru**** 244400 points
    Hello Chao

    In the text above the table, "When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied". Hence 400 Mhz VCO becomes 200MHz before the Divisor is applied.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Prodigy 30 points
    hi,
    Thanks with the reply.
    sorry i made mistake, i know it is 200MHZ.
    the question is why?
    the out put frequency from VCO should be the same as input reference frequency(that is what PLL does). So, the value field where these 66,67 and 50 stands should depend on the input reference frequency.
  • 0 in reply to Chao Huo
    TI__Guru**** 244400 points
    Hello Chao,

    Please explain how the VCO would be same as the input reference frequency (and what do you mean by input reference frequency)?

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Prodigy 30 points
    Hi,
    input---> phase detector ---> charge pump ---> VCO ---> output
    | |
    ----------------------------------------------------
    i mean what the PLL does is to make the output signal the same frequency with input signal.
    If we use PLL(set BYPASS=0) to generate the system clock , then the output should depend on the input.
    but in the table it listed the "possible system clock frequencies" is calculated with 200 MHZ, i mean according to my understanding , it should be calculated with the input frequency.
    What is wrong with my understanding?
  • 0 in reply to Chao Huo
    TI__Guru**** 244400 points
    Hello Chao,

    When BYPASS=0, then the output of the PLL is VCO. If BYPASS=1 then the output is the same as the input clock source.

    Regards
    Amit