• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 32 subscribers
  • Views 1079 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

QSSI to parallel DAC-s

Djedjica
Intellectual 870 points

Other Parts Discussed in Thread: TM4C1294NCPDT

Hello everyone, 

I'm working with ek tm4c1294 since I am planning to use tm4c1294ncpdt in company's project. Now I am researching on how to write code for this controller to write parallel data for several DAC-s connected in parallel to the lines of QSSI peripheral. I was searching through datasheet but still I'm not quite clear on which data goes to which line, so if I send 4 bits at one clock tick each bit goes to the different line. Am I right? And I am sending the array of bytes for example. I am a little bit confused on how to arrange values so that each DAC gets data that it should get. Am I making sense to you?

  • 0
    TI__Guru**** 244440 points
    Hello Djedjica,

    If you are referring to the Quad Mode, then the byte is split and sent on each of the 4 Data Lines. As an example a byte of data will be sent as

    XDAT0 <= BIT 4 BIT 0
    XDAT1 <= BIT 5 BIT 1
    XDAT2 <= BIT 6 BIT 2
    XDAT3 <= BIT 7 BIT 3

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Guru 11940 points

    In other words: QSSI was designed with rapid parallel access of serial Flash ICs in mind, rather than a generic approach as you suggest. I didn't read the according spec., but I would be surprised if you could get your DACs working reliably with QSSI.

  • 0 in reply to Amit Ashara
    Intellectual 870 points

    Hello Mr. Ashara, 

    thank you for the quick response, I was assuming it goes that way but I couldn't find it anywhere written explicitly that way, so I wanted to make sure.

    If I can ask one more thing regarding this TI products, I managed to get ethernet data and using DMA send it directly to QSSI, now since data gets shifted this way on QSSI and may DAC-s all need to display different signals on their output, I assume great data manipulation needs to be done to make sure DAC-s get right data without losing any bits. What is the fastest way to manipulate processor input so that various data signals get sorted in a way that they are mixed every fourth bit belongs to different analog input. If I explained right, so in short four analog inputs get shifted in ethernet and from ethernet to QSSI all using uDMA, when should I arrange data bytes to have result byte contain only two bits of one analog input. I have some kind of image in my head on how to do it but I would use processor and I'm afraid it would slow everything down. Just in general.

    Regards, 

    Djedjica

  • 0 in reply to Djedjica
    TI__Guru**** 244440 points
    Hello Djedjica,

    You would need to process the data in the uDMA buffer before configuring the uDMA to send the data to the SSI Module. Of course processing would be required, but then unless, the data is sent from the Ethernet Source in a format QSSI can send it to the DAC's w/o processing, this is required.

    Regards
    Amit
  • 0 in reply to Amit Ashara
    Intellectual 870 points
    Hello Mr. Ashara,
    I'm having again some kind of doubts regarding this project. So I am embedding this solution connecting one QSSI output to DAC, data that will be sent to QSSI is in QSSI format, It is read from QSSI on the other side so I supposed they will go out in the right way. But I'm having some kind of difficulties with FSS, since QSSI characteristics it goes up and down every 2 clock ticks (since 2 CLK ticks are needed to throw out 8-bit data on QSSI?). Since DAC is connected to the single QSSI DAT line I need FSS to tick once after 16 clock ticks (DAC receives 16-bit data). I was trying to use GPIO and send it up and down after 8 QSSI transfers (x2 clock ticks is 16 bits in DAC, one QSSI transfer is 2 clock ticks, or 2 bits on DAC). But I'm having difficulties with syncing everything. What is the best way to do this, to set FSS to work manually? Timers? Main loop or?
    Please have in mind that this data shifting is accomplished across uDMA directly from ethernet descriptors so? I am not sure how much it would be reliable to have this work on the processor while uDMA does shifting to QSSI output FIFO.

    Kind regards,
    Djedjica
  • 0 in reply to Djedjica
    Guru 117855 points
    Pardon - but you weave so complex a puzzle - do you not?

    Will it not prove far simpler - and much faster - for you to target ONE Small GOAL - rather than SO MANY?

    I'd suggest that you limit your attack to single DAC - w/out µDMA and ethernet - and prove that you can make that work!

    Too many variables - too much complexity - and NO solid foundation - is not the way to, "Quell one's doubts." (but a great means to increase them...)
  • 0 in reply to cb1_mobile
    Intellectual 870 points
    Hello Mr. cb1
    Yes I am aware of that, but my main requirement is multiple realtime channels that will show different analog signals out.
    DAC is working with TI SSI I already tested it although I haven't tested jet if right data will be shown on SSI if data is sent from the second board via Eth, I will test it today, with DAC, I was testing that last week without DAC-s but only verified signals on the oscilloscope. Thank You for this remark. But in production I need QUAD since I have 8 DAC connected to the board, I assumed it would be an easier solution and faster instead of using 4 SSI peripheral and adjust data for 2-channel DACs, I want to use 2 QUAD-s.
    Kind regards,
    Jelena
  • 0 in reply to Djedjica
    Guru 117855 points

    Thank you - in many years of (successful) design/development, test/verify - the KISS method has proved itself, endlessly. And nearly each/every time firm/I bypass KISS - the end result takes longer - proves not as robust! (we thus trade speed for security/sureness)

    It's clear that we (you & I) have the same "end roadmap" (your project's success) but differ in, "How best to realize?"

    Firm/my observation - one small, measurable tech-step at a time - w/full documentation of set-up & results.   By "clumping/combining" so many design elements - do you not, "Hold your Quad DAC testing HOSTAGE" to earlier stages - and your full/complete understanding (and mastery) of them all?   Is that wise?  Is that efficient?   KISS rules - for (just) such reasons!

    Proceeding w/too many balls (or design elements) "in the air" yields unpleasant results - both here and in (more conventional) circus...

  • 0 in reply to Djedjica
    TI__Guru**** 244440 points
    Hello Djedjica

    To extend the FSS for the duration of the transfer, the EOM bit must not be set till the last byte is to be sent. Also the FSSHLDFRM bit must be set before the transaction

    Regards
    Amit