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PWM output when disabling timer

Other Parts Discussed in Thread: TM4C1231D5PM

Hello,


I have a PWM running on a TM4C1231D5PM microcontroller using T0CCP0 pin and Timer0-A. The pwm pin is driving a SEPIC voltage converter. This works just fine.

But whenever I want to stop the PWM (by disabling the timer), I noticed that the output on the pin will freeze on the value that it was in. So when the output was in LOW state when I disable the timer, all is fine. But when the output was in HIGH state when I disable the timer, it will stay HIGH forever and cause a short circuit on my voltage converter connected to it.

Now my question: Is this behaviour wanted and correct? Is there some way to configure what state the pin should go in when the timer is disabled?

Thanks and regards

Renato


The code I use to configure my pwm:

----------------------------------------------------------------------

// Enable the peripherals (Timer0 und Port B)
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
MAP_SysCtlDelay(5);

// set GPIO Pin muxing to select PWM0 for Pin PB6
MAP_GPIOPinConfigure(GPIO_PB6_T0CCP0);

// configure pin as timer pin
MAP_GPIODirModeSet(GPIO_PORTB_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
MAP_GPIOPinTypeTimer(GPIO_PORTB_BASE, GPIO_PIN_6);

// Set timer prescaler to 0 (max speed)
MAP_TimerPrescaleSet(TIMER0_BASE, TIMER_A, 0);

// Configure Timer as PWM
MAP_TimerConfigure(TIMER0_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PWM);

// non-inverting output (active high --> timer disabled = low)
MAP_TimerControlLevel(TIMER0_BASE, TIMER_A, FALSE);

// Timer should run on in debug mode
MAP_TimerControlStall(TIMER0_BASE, TIMER_A, FALSE);

// Set PWM periode (timer load value) to 160kHz
PWM_PERIOD = (MAP_SysCtlClockGet() / 160000) - 1;
MAX_INTEGRAL = (PWM_PERIOD - 1) << 16;
MAP_TimerLoadSet(TIMER0_BASE, TIMER_A, PWM_PERIOD);

// Set Duty Cycle to 0%
MAP_TimerMatchSet(TIMER0_BASE, TIMER_A, PWM_PERIOD-1);

// Reload of Match-Register (MRSU) and Relaod-Registers (ILD) should only be done after timeout
HWREG(TIMER0_BASE + TIMER_O_TAMR) |= (TIMER_TAMR_TAMRSU | TIMER_TAMR_TAILD);

// Disable PWM (stop)
MAP_TimerDisable(TIMER0_BASE, TIMER_A);


// Set Duty Cycle to 25% and start
MAP_TimerMatchSet(TIMER0_BASE, TIMER_A, PWM_PERIOD - (PWM_PERIOD >> 2));
//Enable PWM (start)
MAP_TimerEnable(TIMER0_BASE, TIMER_A);



  • Three (potential) ways to resolve:

    • Read the state of the timer output pin & (only) allow disabling when that pin goes low
    • Accept the variability of the pin and, "Repurpose that pin" from Timer Output to GPIO - then drive it low.
    • Add a series R between Timer Output & Sepic input AND employ a (spare) GPIO (config'ed as Open Drain) to "pull-down" Timer Output when disabled.

    In years here I cannot recall such an issue - the Timer generated PWM is so simple & effective - but the (fine detail) you seek appears beyond its capabilities.

    Dawns that (maybe) a Timer Reset may force an output low - this is pure "SWAG" - you'll have to test/verify...

  • Thank you for your suggestions...

    I've found a similar way to solve the problem:
    By setting the PLO-bit in the configuration register I am now able to bring the duty cycle to a real zero when setting match value same as reload value. After that I only have to wait for at least one pwm period (what is a acceptable short time wit 160kHz pwm) and then I can disable the timer without risk, because the signal is zero within the complete pwm period.

    regards,
    Renato