Other Parts Discussed in Thread: TM4C1292NCPDT
Hello community,
I have one question, just to make things right, some clarification.
OK, I use TM4C1292NCPDT, using QSSI I will read some data from ADC-s. In ADC sample rate is up to 1MSps, Sample is 16 bits, that means I need at least 16MHz on QSSI clock in controller QSSI. Since I will be running controller at 120 MHz I can set QSSI to 16 000 000 if master right? Since if I got it right for slave it needs to be at least 12 times slower than controller clock. It is not the problem to set controller as SSI master even if my controller all that will do is read this data and using uDMA shift this data to ethernet MAC?