N2HET problem - simulation vs reality

Hugo,

What does your silicon do that is different than the simulator?

The other day I ran into an issue where the silicon was behaving differently because I forgot to branch to address 0 at the end of my program. The IDE's simulator seems to be more forgiving of this while silicon keeps running through the uninitialized HET RAM and gives an error.

Pls. post the register file view of the HET on silicon and I'll see if I can decipher what may be the issue ..

Hello Anthony,

sorry for the delay of my answer but I was out for one week.

So, my program  generates "X" clocks after the occurrence of a rising edge.

In the silicon, I see that sometimes the clock pin misses one edge. By order words, between two LR cycles the cock pin must perform a rising or falling edge. I saw through an oscilloscope that sometimes it misses that edge and stays high or low one LR cycle. These "sometimes" seems random...

These pins are connected to another chip. 


In which state do you want to see the registers? In the initialization?

Hi Hugo,

Hmm. That sounds different than I was thinking but ok. Still good to look at the registers.
Would be good to see them both:
a) after initialization
b) after the problem occurs

We're looking here for something that isn't modeled. The System C model under the HET IDE is behavioral and not structural so there could be differences especially in terms of behavior if executing from say uninitialized RAM or using a register that was not initialized.

When your program generates X edges - and you see an edge missed, where does this occur? In the middle of the "X" edges? Or at the beginning or end of the X edges?

Picture would be pretty helpful - if you send a shot of the execution from both the IDE and from the silicon.
If this is sensitive you can send it to me privately by email on this forum.

Best Regards,
Anthony